Data Sheet

Ethernet Controller I210 — Programming Interface
470
8.15 Time Sync Register Descriptions
8.15.1 Rx Time Sync Control Register - TSYNCRXCTL (0xB620;RW)
8.15.2 Rx Timestamp Low - RXSTMPL (0xB624; RO)
8.15.3 Rx Timestamp High - RXSTMPH (0xB628; RO)
Field Bit(s) Initial Value Description
RXTT(RO) 0 0x0
Rx Timestamp Valid
Bit is set when a valid value for Rx timestamp is captured in the Rx timestamp
registers. Bit is cleared by read of Rx timestamp high register (RXSTMPH)).
Type 3:1 0x0
Type of Packets to Timestamp.
000b = Timestamp L2 (V2) packets with MessageType as defined by MSGT field in the
TSYNCRXCFG register as well as DELAY_REQ and DELAY_RESP packets.
001b = Timestamp L4 (V1) packets with Control as defined by CTRLT field in the
TSYNCRXCFG register.
010b = Timestamp V2 (L2 and L4) packets with MessageType as defined by MSGT
field in the TSYNCRXCFG register as well as DELAY_REQ and DELAY_RESP packets.
100b = timestamp all packets.
101b = Timestamp all V2 packets which have a MessageType bit 3 zero, which means
timestamp all event packets.
011b, 110b and 111b = Reserved
En 4 0b
Enable Rx Timestamp
0b = Timestamping disabled.
1b = Timestamping enabled.
RSV 31:5 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
RTSL 29:0 0x0 Rx timestamp LSB value (defined in ns units).
Zero 31:30 0x0 Zero bits.
Field Bit(s) Initial Value Description
RTSH 31:0 0x0 Rx timestamp MSB value (defined in second units).