Data Sheet

Ethernet Controller I210 — Programming Interface
466
8.13.2 Tx DCA Control Registers - TXCTL (0xE014 + 0x40*n [n=0...3];
R/W)
Field Bit(s) Initial Value Description
Tx Descriptor Fetch
TPH EN
1
1. Both the DCA Enable bit and the TPH Enable bit should not be set for the same type of traffic.
00b
Transmit Descriptor Fetch TPH Enable.
When set, hardware enables TPH for all Tx descriptors fetch from memory. When
cleared, hardware does not enable TPH for descriptor fetches. This bit is cleared as a
default.
Tx Descriptor
Writeback TPH EN
10b
Transmit Descriptor Writeback TPH Enable.
When set, hardware enables TPH for all Tx descriptors written back into memory.
When cleared, hardware does not enable TPH for descriptor write-backs. This bit is
cleared as a default. The hint used is the hint set in the Socket ID field.
Reserved 2 0b
Reserved.
Write 0b, ignore on read.
Tx Packet TPH EN 3 0b
Transmit Packet TPH Enable.
When set, hardware enables TPH for all Ethernet payloads read from memory. When
cleared, hardware does not enable TPH for Ethernet payloads. This bit is cleared as a
default.
Reserved 4 0b
Reserved.
Write 0b, ignore on read.
Tx Descriptor DCA
EN
1
50b
Descriptor DCA Enable.
When set, hardware enables DCA for all Tx descriptors written back into memory.
When cleared, hardware does not enable DCA for descriptor write backs. This bit is
cleared as a default and also applies to head write back when enabled.
Reserved 7:6 00b
Reserved.
Write 00b, ignore on read.
TXdescRDNSen 8 0b
Tx Descriptor Read No Snoop Enable.
This bit must be reset to 0b to ensure correct functionality (unless the software
device driver has written this bit with a write-through instruction).
Note: When TPH is enabled No Snoop bit should be 0b.
TXdescRDROEn 9 1b Tx Descriptor Read Relax Order Enable.
TXdescWBNSen 10 0b
Tx Descriptor Write-Back No Snoop Enable.
This bit must be reset to 0b to ensure correct functionality of descriptor write-back.
Also applies to head write-back, when enabled.
Note: When TPH is enabled No Snoop bit should be 0b.
TXdescWBROen 11 1b
Tx Descriptor Write Back Relax Order Enable.
Applies to head write back, when enabled.
TXDataReadNSEn 12 0b
Tx Data Read No Snoop Enable.
Note: When TPH is enabled No Snoop bit should be 0b.
TXDataReadROEn 13 1b Tx Data Read Relax Order Enable.
Reserved 23:14 0b
Reserved
Write 0 ignore on read.
CPUID 31:24 0x0
Physical ID
Legacy DCA capable platforms - the device driver, upon discovery of the physical CPU
ID and CPU Bus ID, programs the CPUID field with the Physical CPU and Bus ID
associated with this Tx queue.
DCA 1.0 capable platforms - the device driver programs a value, based on the
relevant APIC ID, associated with this Tx queue.
Refer to Table 3.1.3.1.2.3 for details
TPH capable platforms - the device driver programs a value, based on the relevant
Socket ID, associated with this transmit queue.
Note that for TPH platforms, bits 31:27 of this field should always be set to zero.
Refer to Section 7.7.2 for details.