Data Sheet

Programming Interface — Ethernet Controller I210
465
Note: In order to keep compatibility withprevious devices, for queues 0-3, these registers are
aliased to addresses 0x2814, 0x2914, 0x2A14 and 0x2B14, respectively.
RXdescRead
NSEn
80b
Receive Descriptor Read No Snoop Enable.
This bit must be reset to 0b to ensure correct functionality (except if the software
driver can guarantee the data is present in the main memory before the DMA process
occurs).
Note: When TPH is enabled, the No Snoop bit should be 0b.
RXdescRead
ROEn
9 1b Receive Descriptor Read Relax Order Enable.
RXdescWBNSen 10 0b
Receive Descriptor Write-Back No Snoop Enable.
This bit must be reset to 0b to ensure correct functionality of descriptor write back.
Note: When TPH is enabled No Snoop bit should be 0b.
RXdescWBROen
(RO)
11 0b
Receive Descriptor Write-Back Relax Order Enable.
This bit must be reset to 0b to ensure correct functionality of descriptor write back.
RXdataWrite
NSEn
12 0b
Receive Data Write No Snoop Enable (header replication: header and data).
When set to 0b, the last bit of the Packet Buffer Address field in the advanced receive
descriptor is used as the LSB of the packet buffer address (A0), thus enabling Byte
alignment of the buffer.
When set to 1b, the last bit of the Packet Buffer Address field in advanced receive
descriptor is used as the No-Snoop Enabling (NSE) bit (buffer is Word aligned). If also
set to 1b, the NSE bit determines whether the data buffer is snooped or not.
Note: When TPH is enabled No Snoop bit should be 0b.
RXdataWrite
ROEn
13 1b Receive Data Write Relax Order Enable (header replication: header and data).
RxRepHeader
NSEn
14 0b
Receive Replicated/Split Header No Snoop Enable.
This bit must be reset to 0b to ensure correct functionality of header write to host
memory.
Note: When TPH is enabled, the No Snoop bit should be 0b.
RxRepHeader
ROEn
15 1b Receive Replicated/Split Header Relax Order Enable.
Reserved 23:16 0x0
Reserved.
Write 0x0, ignore on read.
CPUID 31:24 0x0
Physical ID.
Legacy DCA capable platforms. The software device driver, upon discovery of the
physical CPU ID and CPU Bus ID, programs the CPUID field with the Physical CPU and
Bus ID associated with this Rx queue.
DCA 1.0 capable platforms. The software device driver programs a value, based on the
relevant APIC ID, associated with this Tx queue.
Refer to Table 3.1.3.1.2.3 for details.
TPH capable platforms. The device driver programs a value, based on the relevant
Socket ID, associated with this receive queue.
Note that for TPH platforms, bits 31:27 of this field should always be set to zero. Refer
to Section 7.7.2 for details.
Field Bit(s) Initial Value Description