Data Sheet

Ethernet Controller I210 — Programming Interface
464
8.13 DCA and TPH Register Descriptions
8.13.1 Rx DCA Control Registers - RXCTL (0xC014 + 0x40*n [n=0...3];
R/W)
Note: Rx data write no-snoop is activated when the NSE bit is set in the receive descriptor.
Note: Both the DCA Enable bit and TPH Enable bit should not be set for the same type of traffic.
DataTranARB 8 0x0
Data Transmit Arbitration.
0b = Strict Priority.
1b = Credit Shaper Algorithm.
Relevant only if TransmitMode is set to 1b (Qav).
DataTranTIM 9 0x0
Data Launch Time Valid.
Relevant only if TransmitMode is set to 1b (Qav).
SP_WAIT_SR 10 0x0
When set to 1b, the SP queues wait for the SR queues to make sure the SR
launch time is always guaranteed.
Reserved 15:11 0x0 Reserved.
FetchTimDelta 31:16 0x0
Fetch Time Delta.
This field holds the value to be reduced from the launch time for fetch time
decision. The FetchTimeDelta value is defined in 32 ns granularity.
Relevant only if TransmitMode is set to 1b (Qav).
Field Bit(s) Initial Value Description
Rx Descriptor
Fetch TPH EN
00b
Receive Descriptor Fetch TPH Enable.
When set, hardware enables TPH for all Rx descriptors fetch from memory. When
cleared, hardware does not enable TPH for descriptor fetches. This bit is cleared as a
default.
Rx Descriptor
Writeback TPH EN
10b
Receive Descriptor Writeback TPH Enable.
When set, hardware enables TPH for all Rx descriptors written back into memory.
When cleared, hardware does not enable TPH for descriptor write-backs. This bit is
cleared as a default. The hint used is the hint set in the Socket ID field.
Rx Header TPH EN 2 0b
Receive Header TPH Enable.
When set, hardware enables TPH for all received header buffers. When cleared,
hardware does not enable TPH for Rx headers. This bit is cleared as a default. The hint
used is the hint set in the Socket ID field.
Rx Payload TPH EN 3 0b
Receive Payload TPH Enable.
When set, hardware enables TPH for all Ethernet payloads written into memory. When
cleared, hardware does not enable TPH for Ethernet payloads. This bit is cleared as a
default. The hint used is the hint set in the Socket ID field.
Reserved 4 0b
Reserved.
Write 0b, ignore on read.
Rx Descriptor
DCA EN
50b
Descriptor DCA Enable.
When set, hardware enables DCA for all Rx descriptors written back into memory.
When cleared, hardware does not enable DCA for descriptor write-backs. This bit is
cleared as a default.
Rx Header DCA EN 6 0b
Receive Header DCA Enable.
When set, hardware enables DCA for all received header buffers. When cleared,
hardware does not enable DCA for Rx headers. This bit is cleared as a default.
Rx Payload DCA EN 7 0b
Receive Payload DCA Enable.
When set, hardware enables DCA for all Ethernet payloads written into memory. When
cleared, hardware does not enable DCA for Ethernet payloads. This bit is cleared as a
default.
Field Bit(s) Initial Value Description