Data Sheet

Ethernet Controller I210 — Programming Interface
462
8.12.16 Tx Descriptor Completion Write-Back Address Low - TDWBAL
(0xE038 + 0x40*n [n=0...3]; R/W)
Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x3838, 0x3938, 0x3A38 and 0x3B38, respectively.
8.12.17 Tx Descriptor Completion Write-Back Address High - TDWBAH
(0xE03C + 0x40*n [n=0...3];R/W)
Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x383C, 0x393C, 0x3A3C and 0x3B3C, respectively.
8.12.18 Tx Qav Hi Credit TQAVHC (0x300C+ 0x40*n [n=0...1];R/W)
Field
1
1. Software should program the TDWBAL[n] register only when a queue is disabled (TXDCTL[n].Enable = 0b).
Bit(s) Initial Value Description
Head_WB_En 0 0b
Head Write-Back Enable.
1b = Head write back is enabled.
0b = Head write back is disabled.
When head_WB_en is set, TXDCTL.SWFLSH is ignored and no descriptor write back is
executed.
WB_on_EITR 1 0b When set, a head write back is done upon EITR expiration.
HeadWB_Low 31:2 0x0
Bits 31:2 of the head write-back memory location (Dword aligned). The last 2 bits of
this field are ignored and are always interpreted as 00b, meaning that the actual
address is Qword aligned.
Bits 1:0 are always 00b.
Field
1
1. Software should program the TDWBAH[n] register only when a queue is disabled (TXDCTL[n].Enable = 0b).
Bit(s) Initial Value Description
HeadWB_High 31:0 0x0 Highest 32 bits of the head write-back memory location.
Field Bit(s) Initial Value Description
HiCredit 31:0 0x0
Hi Credit Value.
Maximum number of credits that this queue can accumulate. See
Section 7.2.7.6 for a description of how this field should be calculated.
Relevant only if TransmitMode is set to 1b (Qav).