Data Sheet

Programming Interface — Ethernet Controller I210
461
Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x3828, 0x3928, 0x3A28 and 0x3B28, respectively.
WTHRESH 20:16 0x0
Write-Back Threshold.
Controls the write-back of processed transmit descriptors. This threshold refers to the
number of transmit descriptors in the on-chip buffer that are ready to be written back
to host memory. In the absence of external events (explicit flushes), the write-back
occurs only after at least WTHRESH descriptors are available for write-back.
Possible values for this field are 0 to 23.
Note: Since the default value for write-back threshold is 0b, descriptors are
normally written back as soon as they are processed. WTHRESH must be
written to a non-zero value to take advantage of the write-back bursting
capabilities of the I210.
Reserved 23:21 0x0 Reserved.
Reserved 24 0b
Reserved.
Write 0b, ignore on read.
ENABLE 25 0b
Transmit Queue Enable.
When set, this bit enables the operation of a specific transmit queue.Setting this bit
initializes the Tail and Head registers (TDT[n] and TDH[n]) of a specific queue. Until
then, the state of the queue is kept and can be used for debug purposes.
When disabling a queue, this bit is cleared only after all transmit activity on this queue
is stopped.
Note: When transmit queue is enabled and descriptors exist, descriptors and data
are fetched immediately. Actual transmit activity on port starts only if the
TCTL.EN bit is set.
SWFLSH 26 0b
Transmit Software Flush.
This bit enables software to trigger descriptor write-back flushing, independently of
other conditions.
This bit must be written to 1b and then to 0b after a write-back flush is triggered.
Note: When working in head write-back mode (TDWBAL.Head_WB_En = 1b)
TDWBAL.WB_on_EITR bit should be set for a transmit descriptor flush to
occur.
Priority 27 0b
Transmit Queue Priority.
0b = Low priority.
1b = High priority.
When set, transmit DMA resources are always allocated to the queue before low
priority queues. Arbitration between transmit queues with the same priority is done in
a Round Robin (RR) fashion or in most empty fashion set by the
TQAVCTRL.DataFetchARB register.
HWBTHRESH 31:28 0x0
Transmit Head Write-back Threshold.
If the value of field is greater than 0x0, the head write-back to host occurs only when
the amount of internal pending write backs exceeds this threshold. Refer to
Section 7.2.4 for additional information.
Note: When activating this mode the WB_on_EITR bit in the TDWBAL register
should be set to guarantee a write back after a timeout even if the threshold
has not been reached.
Field Bit(s) Initial Value Description