Data Sheet

Ethernet Controller I210 — Programming Interface
460
8.12.14 Transmit Descriptor Tail - TDT (0xE018 + 0x40*n [n=0...3]; R/
W)
These registers contain the tail pointer for the transmit descriptor ring and points to a 16-byte datum.
Software writes the tail pointer to add more descriptors to the transmit ready queue. Hardware
attempts to transmit all packets referenced by descriptors between head and tail.
Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x3818, 0x3918, 0x3A18 and 0x3B18, respectively.
8.12.15 Transmit Descriptor Control - TXDCTL (0xE028 + 0x40*n
[n=0...3]; R/W)
These registers control the fetching and write-back operations of transmit descriptors. The three
threshold values are used to determine when descriptors are read from and written to host memory.
The values are in units of descriptors (each descriptor is 16 bytes).
Since write-back of transmit descriptors is optional (under the control of RS bit in the descriptor), not
all processed descriptors are counted with respect to WTHRESH. Descriptors start accumulating after a
descriptor with RS set is processed. In addition, with transmit descriptor bursting enabled, some
descriptors are written back that did not have RS set in their respective descriptors.
Note: When WTHRESH = 0x0, only descriptors with the RS bit set are written back.
Field Bit(s) Initial Value Description
TDT 15:0 0x0 Transmit Descriptor Tail.
Reserved 31:16 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
PTHRESH 4:0 0x0
Prefetch Threshold.
Controls when a prefetch of descriptors is considered. This threshold refers to the
number of valid, unprocessed transmit descriptors the I210 has in its on-chip buffer. If
this number drops below PTHRESH, the algorithm considers pre-fetching descriptors
from host memory. However, this fetch does not happen unless there are at least
HTHRESH valid descriptors in host memory to fetch.
Note: When PTHRESH is 0x0 a transmit descriptor fetch operation is done when any
valid descriptors are available in host memory and space is available in
internal buffer.
Reserved 7:5 0x0
Reserved.
Write 0x0, ignore on read.
HTHRESH 12:8 0x0
Host Threshold.
Prefetch of transmit descriptors is considered when number of valid transmit
descriptors in host memory is at least HTHRESH.
Note: HTHRESH should be given a non zero value each time PTHRESH is used.
Reserved 15:13 0x0
Reserved.
Write 0x0, ignore on read.