Manualshelf

Data Sheet

ManualsBrandsIntel ManualsComputing & OfficeIntel Intel Ethernet Server Adapter I210-T1 - Network adapter 1 Gbps LAN (10/100/1000 Mbps), PCI-Express
451452453454455456457458459460
Programming Interface — Ethernet Controller I210
459
8.12.11 Transmit Descriptor Base Address High - TDBAH (0xE004 +
0x40*n [n=0...3]; R/W)
These registers contain the upper 32 bits of the 64-bit descriptor base address.
Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x3804, 0x3904, 0x3A04 and 0x3B04, respectively.
8.12.12 Transmit Descriptor Ring Length - TDLEN (0xE008 + 0x40*n
[n=0...3]; R/W)
These registers contain the descriptor ring length. The registers indicates the length in bytes and must
be 128-byte aligned.
Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x3808, 0x3908, 0x3A08 and 0x3B08, respectively.
8.12.13 Transmit Descriptor Head - TDH (0xE010 + 0x40*n [n=0...3];
RO)
These registers contain the head pointer for the transmit descriptor ring. It points to a 16-byte datum.
Hardware controls this pointer.
Note: The values in these registers might point to descriptors that are still not in host memory. As a
result, the host cannot rely on these values in order to determine which descriptor to release.
Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x3810, 0x3910, 0x3A10 and 0x3B10, respectively.
Field
1
1. Software should program the TDBAH[n] register only when a queue is disabled (TXDCTL[n].Enable = 0b).
Bit(s) Initial Value Description
TDBAH 31:0 X Transmit Descriptor Base Address [63:32].
Field
1
1. Software should program the TDLEN[n] register only when a queue is disabled (TXDCTL[n].Enable = 0b).
Bit(s) Initial Value Description
Zero 6:0 0x0
Ignore on writes.
Read back as 0x0.
LEN 19:7 0x0
Descriptor Ring Length (number of 8 descriptor sets).
Note: Maximum allowed value in TDLEN field 19:0 is 0x80000 (32K
descriptors).
Reserved 31:20 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
TDH 15:0 0x0 Transmit Descriptor Head.
Reserved 31:16 0x0
Reserved.
Write 0x0, ignore on read.