Data Sheet

Ethernet Controller I210 — Programming Interface
458
8.12.8 DMA TX Max Total Allow Size Requests - DTXMXSZRQ (0x3540;
RW)
This register limits the allowable size of concurrent outstanding Tx read requests from the host memory
on the PCIe. Limiting the size of concurrent outstanding PCIe requests allows low latency packet read
requests to be serviced in a timely manner, as the low latency request is serviced right after current
outstanding requests are completed.
8.12.9 DMA TX Maximum Packet Size - DTXMXPKTSZ (0x355C; RW)
This register limits the total number of data bytes that might be transmitted in a single frame. Reducing
packet size enables better utilization of transmit buffer.
8.12.10 Transmit Descriptor Base Address Low - TDBAL (0xE000 +
0x40*n [n=0...3]; R/W)
These registers contain the lower 32 bits of the 64-bit descriptor base address. The lower 7 bits are
ignored. The Transmit Descriptor Base Address must point to a 128-byte aligned block of data.
Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x3800, 0x3900, 0x3A00 and 0x3B00, respectively.
Field Bit(s) Initial Value Description
Max_bytes_num_req 11:0 0x10
Maximum allowable size of concurrent Tx outstanding requests on PCIe.
Field defines maximum size in 256 byte resolution of outstanding Tx requests
to be sent on PCIe. If total amount of outstanding Tx requests is higher than
defined in this field, no further Tx outstanding requests are sent.
Reserved 31:12 0x0 Reserved.
Field Bit(s) Initial Value Description
MAX_TPKT_SIZE 8:0 0x98
Maximum transmit packet size that is allowed to be transmitted by the driver.
Value entered is in 64 Bytes resolution.
Notes:
1. Default value enables transmission of maximum sized 9,728-byte Jumbo
frames.
2. Values programmed in this field should not exceed 9,728 bytes.
3. Value programmed should not exceed the Tx buffers size programmed in
the TXPBSIZE register.
Reserved 31:9 0x0
Reserved.
Write 0x0, ignore on read.
Field
1
1. Software should program the TDBAL[n] register only when a queue is disabled (TXDCTL[n].Enable = 0b).
Bit(s) Initial Value Description
Lower_0 6:0 0x0
Ignored on writes.
Returns 0x0 on reads.
TDBAL 31:7 X Transmit Descriptor Base Address Low.