Data Sheet

Programming Interface — Ethernet Controller I210
457
8.12.6 DMA TX TCP Flags Control Low - DTXTCPFLGL (0x359C; RW)
This register holds the buses that AND the control flags in TCP header for the first and middle
segments of a TSO packet.
Refer to Section 7.2.4.7.1 and Section 7.2.4.7.2 for details on the use of
this register.
8.12.7 DMA TX TCP Flags Control High - DTXTCPFLGH (0x35A0; RW)
This register holds the buses that AND the control flags in TCP header for the last segment of a TSO
packet. Refer to Section 7.2.4.7.3 for details of use of this register.
Field Bit(s) Initial Value Description
Reserved 1:0 0x0
Reserved.
Write 0x0, ignore on read.
Enable_spoof_queue 2 0b
Enable Spoofing Queue.
0b = Disable queue that exhibited spoofing behavior.
1b = Do not disable port that exhibited spoofing behavior.
Reserved 3 0x0
Reserved.
Write 0x0, ignore on read.
OutOfSyncDisable 4 0b
Disable Out Of Sync Mechanism.
0b = Out Of Sync mechanism is enabled.
1b = Out Of Sync mechanism is disabled.
Reserved 6:5 0 Reserved.
Count CRC 7 1b
If set, the CRC is counted as part of the packet bytes statistics in per
Queue statistics (PQGORC, PQGOTC, PQGORLBC and PQGOTLBC).
Reserved 31:8 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
TCP_flg_first_seg 11:0 0xFF6
TCP Flags First Segment.
Bits that are used to execute an AND operation with the TCP flags in the TCP
header in the first segment
Reserved 15:12 0x0
Reserved.
Write 0x0, ignore on read.
TCP_Flg_mid_seg 27:16 0xF76
TCP Flags middle segments.
Bits that are used to execute an AND operation with the TCP flags in the TCP
header in the middle segments.
Reserved 31:28 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
TCP_Flg_lst_seg 11:0 0xF7F
TCP Flags Last Segment.
Bits that are used to execute an AND operation with the TCP flags at TCP header
in the last segment.
Reserved 31:12 0x0
Reserved.
Write 0x0, ignore on read.