Data Sheet

Interconnects—Ethernet Controller I210

Table 3-8 lists software configuration for the No-Snoop and Relaxed Ordering bits for LAN traffic when

I/OAT 2 is enabled.

3.1.4.5.4.1 No-Snoop Option for Payload

Under certain conditions, which occur when I/OAT is enabled, software knows that it is safe to transfer

(DMA) a new packet into a certain buffer without snooping on the front-side bus. This scenario typically

occurs when software is posting a receive buffer to hardware that the CPU has not accessed since the

last time it was owned by hardware. This might happen if the data was transferred to an application

buffer by the I/OAT DMA engine.

In this case, software should be able to set a bit in the receive descriptor indicating that the I210

should perform a no-snoop DMA transfer when it eventually writes a packet to this buffer.

When a non-snoop transaction is activated, the TLP header has a non-snoop attribute in the

Transaction Descriptor field.

This is triggered by the NSE bit in the receive descriptor. Refer to Section 7.1.4.2.

3.1.4.5.5 TLP Processing Hint (TPH)

The TPH bit can be set to provide information to the root complex about the cache in which the data

should be stored or from which the data should be read as described in Section 7.7.2.

TPH is enabled via the TPH Requester Enable field in the TPH control register of the configuration space

(refer to Section 9.5.3.3). Setting of the TPH bit for different type of traffic is listed in Table 7-61.

Table 3-8. LAN Traffic Attributes

Transaction No-Snoop Relaxed Ordering Comments

Rx Descriptor Read N Y

Rx Descriptor Write-Back N N

Relaxed ordering must never be used

for this traffic.

Rx Data Write Y Y

Refer to Note 1 and

Section 3.1.4.5.4.1

Rx Replicated Header N Y

Tx Descriptor Read N Y

Tx Descriptor Write-Back N Y

Tx TSO Header Read N Y

Tx Data Read N Y

Note:

1. Rx payload no-snoop is also conditioned by the NSE bit in the receive descriptor. Refer to Section 3.1.4.5.4.1.