Data Sheet

Programming Interface — Ethernet Controller I210
449
8.10.22 Redirection Table - RETA (0x5C00 + 4*n [n=0...31]; R/W)
The redirection table is a 128-entry table with each entry being eight bits wide. Only 1 to 3 bits of each
entry are used to store the queue index. The table is configured through the following R/W registers.
Each entry (byte) of the redirection table contains the following:
— Bits [7:3] - Reserved.
— Bits [2:0] - Queue index for all pools or in regular RSS. In RSS only mode, all bits are used.
The contents of the redirection table are not defined following reset of the Memory Configuration
registers. System software must initialize the table prior to enabling multiple receive queues. It can
also update the redirection table during run time. Such updates of the table are not synchronized with
the arrival time of received packets. Therefore, it is not guaranteed that a table update takes effect on
a specific packet boundary.
Note: In case the operating system provides a redirection table whose size is smaller than 128
bytes, the software usually replicates the operating system-provided redirection table to span
the whole 128 bytes of the hardware's redirection table.
8.10.23 DMA VM Offload Register - DVMOLR (0xC038 + 0x40*n[n=0...3];
RW)
This register controls part of the offload and queueing options applied to each queue.
Field Bit(s) Initial Value Description
Entry 0 7:0 0x0
Determines the tag value and physical queue for index 4*n+0
(n=0...31).
Entry 1 15:8 0x0
Determines the tag value and physical queue for index 4*n+1
(n=0...31).
Entry 2 23:16 0x0
Determines the tag value and physical queue for index 4*n+2
(n=0...31).
Entry 3 31:24 0x0
Determines the tag value and physical queue for index 4*n+3
(n=0...31).
31 24 23 16 15 8 7 0
Tag 3 Tag 2 Tag 1 Tag 0
... ... ... ...
Tag 127 ... ... ...
7:3 2:0
Reserved Queue index