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Data Sheet

ManualsBrandsIntel ManualsComputing & OfficeIntel Intel Ethernet Server Adapter I210-T1 - Network adapter 1 Gbps LAN (10/100/1000 Mbps), PCI-Express
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Programming Interface — Ethernet Controller I210
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8.10.17 Receive Address High - RAH (0x5404 + 8*n [n=0...15]; R/W)
These registers contain the upper bits of the 48-bit Ethernet address. The complete address is [RAH,
RAL]. The RAH.AV bit determines whether this address is compared against the incoming packet.
The RAH.ASEL field enables the I210 to perform special filtering on receive packets.
After reset, if an Flash is present, the first register (Receive Address Register 0) is loaded from the IA
field in the Flash with its Address Select field set to 00b and its Address Valid field set to 1b. If no Flash
is present, the Address Valid field is set to 0b and the Address Valid field for all of the other registers is
set to 0b.
Note: The RAH field should be written in network order.
The first receive address register (RAH[0]) is also used for exact match pause frame checking
(DA matches the first register). As a result, RAH[0] should always be used to store the
individual Ethernet MAC address of the I210.
Field Bit(s) Initial Value Description
RAH 15:0 X
Receive address High.
Contains the upper 16 bits of the 48-bit Ethernet address.
ASEL 17:16 X
Address Select.
Selects how the address is to be used in the address filtering.
00b = Destination address (required for normal mode).
01b = Source address.
10b = Reserved.
11b = Reserved.
QSEL 19:18 X
Queue Select.
In Qav mode, indicates which Rx queue should get the packets
matching this MAC address. This field maps to the relevant
queue:
00b = queue0.
01b = queue1.
10b = queue2.
11b = queue3.
Reserved 27:20 0x0
Reserved.
Write 0x0, Ignore on reads
QSEL Enable 28 X
Queue Select Enable.
When set to 1b the value in the QSEL should be used as part of
the queue classification algorithm.
Reserved 30:29 0x0
Reserved.
Write 0x0, ignore on reads.
AV 31 0x0
Address Valid.
Cleared after master reset. If a Flash is present, the Address
Valid field of the Receive Address Register 0 is set to 1b after a
software or PCI reset or Flash read.
In entries 0-15 this bit is cleared by master reset.