Data Sheet
Ethernet Controller I210 ā Programming Interface
444
Figure 8-1 shows the multicast lookup algorithm. The destination address shown represents the
internally stored ordering of the received DA. Note that bit 0 indicated in this diagram is the first on the
wire.
8.10.16 Receive Address Low - RAL (0x5400 + 8*n [n=0...15]; R/W)
While ānā is the exact unicast/multicast address entry and it is equal to 0,1,...15.
These registers contain the lower bits of the 48 bit Ethernet address. All 32 bits are valid.
These registers are reset by a software reset or platform reset. If a Flash is present, the first register
(RAL0) is loaded from the Flash after a software or platform reset.
Note: The RAL field should be written in network order.
Field Bit(s) Initial Value Description
Bit Vector 31:0 X Word wide bit vector specifying 32 bits in the multicast address filter table.
Figure 8-1. Multicast Table Array
Field Bit(s) Initial Value Description
RAL 31:0 X
Receive Address Low.
Contains the lower 32-bit of the 48-bit Ethernet address.
47:40
39:32 31:24
23:16
15:8
7:0
pointer[11:5]
Multicast Table Array
32 x 128
(4096 bit vector)
...
...
pointer[4:0]
word
bit
?
Destination Address
RCTL.MO[1:0]