Data Sheet

Ethernet Controller I210 —Interconnects
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3.1.4.5 Transaction Definition and Attributes
3.1.4.5.1 Max Payload Size
The I210 policy to determine Max Payload Size (MPS) is as follows:
• Master requests initiated by the I210 (including completions) limits MPS to the value defined for the
function issuing the request.
• Target write accesses to the I210 are accepted only with a size of one Dword or two Dwords. Write
accesses in the range of (three Dwords, MPS, etc.) are flagged as UR. Write accesses above MPS
are flagged as malformed.
3.1.4.5.2 Relaxed Ordering
The I210 takes advantage of the relaxed ordering rules in PCIe. By setting the relaxed ordering bit in
the packet header, the I210 enables the system to optimize performance in the following cases:
• Relaxed ordering for descriptor and data reads: When the I210 emits a read transaction, its split
completion has no ordering relationship with the writes from the CPUs (same direction). It should
be allowed to bypass the writes from the CPUs.
• Relaxed ordering for receiving data writes: When the I210 issues receive DMA data writes, it also
enables them to bypass each other in the path to system memory because software does not
process this data until their associated descriptor writes complete.
• The I210 cannot relax ordering for descriptor writes, MSI/MSI-X writes or PCIe messages.
Relaxed ordering can be used in conjunction with the no-snoop attribute to enable the memory
controller to advance non-snoop writes ahead of earlier snooped writes.
Relaxed ordering is enabled in the I210 by clearing the RO_DIS bit in the CTRL_EXT register. Actual
setting of relaxed ordering is done for LAN traffic by the host through the DCA registers.
3.1.4.5.3 Snoop Not Required
The I210 sets the Snoop Not Required attribute bit for master data writes. System logic might provide
a separate path into system memory for non-coherent traffic. The non-coherent path to system
memory provides higher, more uniform, bandwidth for write requests.
Note: The Snoop Not Required attribute does not alter transaction ordering. Therefore, to achieve
maximum benefit from Snoop Not Required transactions, it is advisable to set the relaxed
ordering attribute as well (assuming that system logic supports both attributes). In fact,
some chipsets require that relaxed ordering is set for no-snoop to take effect.
Global no-snoop support is enabled in the I210 by clearing the NS_DIS bit in the CTRL_EXT register.
Actual setting of no snoop is done for LAN traffic by the host through the DCA registers.
3.1.4.5.4 No Snoop and Relaxed Ordering for LAN Traffic
Software might configure non-snoop and relax order attributes for each queue and each type of
transaction by setting the respective bits in the RXCTRL and TXCTRL registers.