Data Sheet

Programming Interface — Ethernet Controller I210
441
Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x2828, 0x2928, 0x2A28 and 0x2B28, respectively.
8.10.10 Receive Queue Drop Packet Count - RQDPC (0xC030 + 0x40*n
[n=0...3]; RW)
Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x2830, 0x2930, 0x2A30 and 0x2B30, respectively.
Packets dropped due to the queue being disabled might not be counted by this register.
8.10.11 Transmit Queue Drop Packet Count - TQDPC (0xE030 + 0x40*n
[n=0...3]; RW)
8.10.12 Receive Checksum Control - RXCSUM (0x5000; R/W)
The Receive Checksum Control register controls the receive checksum off loading features of the I210.
The I210 supports the off loading of three receive checksum calculations: the Packet Checksum, the IP
Header Checksum, and the TCP/UDP Checksum.
Note: This register should only be initialized (written) when the receiver is not enabled (only write
this register when RCTL.RXEN = 0b)
Field Bit(s) Initial Value Description
RQDPC 31:0 0x0
Receive Queue Drop Packet Count.
Counts the number of packets dropped by a queue due to lack of descriptors
available.
Note: Counter wraps around when reaching a value of 0xFFFFFFFF.
Field Bit(s) Initial Value Description
TQDPC 31:0 0x0
Transmit Queue Drop Packet Count.
Counts the number of packets dropped by a queue due to lack of space in the
loopback buffer or due to security (anti-spoof) issues.
A multicast packet dropped by some of the destinations, but sent to others is counted
by this counter.
Note: Counter wraps around when reaching a value of 0xFFFFFFFF.