Data Sheet

Ethernet Controller I210 — Programming Interface
440
8.10.9 Receive Descriptor Control - RXDCTL (0xC028 + 0x40*n
[n=0...3]; R/W)
This register controls the fetching and write-back of receive descriptors. The three threshold values are
used to determine when descriptors are read from and written to host memory. The values are in units
of descriptors (each descriptor is 16 bytes).
Field Bit(s) Initial Value Description
PTHRESH 4:0 0xC
Prefetch Threshold
PTHRESH is used to control when a prefetch of descriptors is considered.
This threshold refers to the number of valid, unprocessed receive
descriptors the I210 has in its on-chip buffer. If this number drops below
PTHRESH, the algorithm considers pre-fetching descriptors from host
memory. This fetch does not happen unless there are at least HTHRESH
valid descriptors in host memory to fetch.
Note: HTHRESH should be given a non zero value each time PTHRESH is
used.
Possible values for this field are 0 to 16.
Reserved 7:5 0x0
Reserved.
Write 0x0, ignore on read.
HTHRESH 12:8 0xA
Host Threshold.
This field defines when a receive descriptor prefetch is performed. Each
time enough valid descriptors, as defined in the HTHRESH field, are
available in host memory a prefetch is performed.
Possible values for this field are 0 to 16.
Reserved 15:13 0x0
Reserved.
Write 0x0, ignore on read.
WTHRESH 20:16 0x1
Write-back Threshold.
WTHRESH controls the write-back of processed receive descriptors. This
threshold refers to the number of receive descriptors in the on-chip buffer
that are ready to be written back to host memory. In the absence of
external events (explicit flushes), the write-back occurs only after at least
WTHRESH descriptors are available for write-back.
Possible values for this field are 0 to 15.
Note: Since the default value for write-back threshold is 1b, the
descriptors are normally written back as soon as one cache line is
available. WTHRESH must contain a non-zero value to take
advantage of the write-back bursting capabilities of the I210.
Note: It’s recommended not to place a value above 0xC in the WTHRESH
field.
Reserved 24:21 0x0 Reserved.
ENABLE 25 0b
Receive Queue Enable.
When set, the Enable bit enables the operation of the specific receive
queue.
1b =Enables queue.
0b =Disables queue. Setting this bit initializes the Head and Tail registers
(RDH[n] and RDT[n]) of the specific queue. Until then, the state of the
queue is kept and can be used for debug purposes.
When disabling a queue, this bit is cleared only after all activity in the
queue has stopped.
Note: When receive queue is enabled and descriptors exist, descriptors
are fetched immediately. Actual receive activity on the port starts
only if the RCTL.RXEN bit is set.
SWFLUSH 26 0b
Receive Software Flush.
Enables software to trigger a receive descriptor write-back flushing,
independently of other conditions.
This bit shall be written to 1b and then to 0b after a write-back flush is
triggered.
Reserved 31:27 0x0 Reserved.