Data Sheet

Programming Interface — Ethernet Controller I210
439
Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x2808, 0x2908, 0x2A08 and 0x2B08, respectively.
8.10.7 Receive Descriptor Head - RDH (0xC010 + 0x40*n [n=0...3]; RO)
The value in this register might point to descriptors that are still not in host memory. As a result, the
host cannot rely on this value in order to determine which descriptor to process.
Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x2810, 0x2910, 0x2A10 and 0x2B10, respectively.
8.10.8 Receive Descriptor Tail - RDT (0xC018 + 0x40*n [n=0...3]; R/W)
This register contains the tail pointers for the receive descriptor buffer. The register points to a 16-byte
datum. Software writes the tail register to add receive descriptors to the hardware free list for the ring.
Note: Writing the RDT register while the corresponding queue is disabled is ignored by the I210.
In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x2818, 0x2918, 0x2A18 and 0x2B18, respectively.
Field
1
1. Software should program the RDLEN[n] register only when a queue is disabled (RXDCTL[n].Enable = 0b).
Bit(s) Initial Value Description
Zero 6:0 0x0
Ignore on writes.
Bits 6:0 must be set to 0x0.
Bits 4:0 always read as 0x0.
LEN 19:7 0x0
Descriptor Ring Length (number of 8 descriptor sets).
Note: Maximum allowed value in RDLEN field 19:0 is 0x80000 (32K
descriptors).
Reserved 31:20 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
RDH 15:0 0x0 Receive Descriptor Head.
Reserved 31:16 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
RDT 15:0 0x0 Receive Descriptor Tail.
Reserved 31:16 0x0
Reserved.
Write 0x0, ignore on read.