Data Sheet

Ethernet Controller I210 — Programming Interface
438
8.10.4 Receive Descriptor Base Address Low - RDBAL (0xC000 + 0x40*n
[n=0...3]; R/W)
This register contains the lower bits of the 64-bit descriptor base address. The lower four bits are
always ignored. The Receive Descriptor Base Address must point to a 128 byte-aligned block of data.
Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x2800, 0x2900, 0x2A00 and 0x2B00, respectively.
8.10.5 Receive Descriptor Base Address High - RDBAH (0xC004 +
0x40*n [n=0...3]; R/W)
This register contains the upper 32 bits of the 64-bit descriptor base address.
Note: In order to keep compatibility with previous devices, for queues 0-3, these registers are
aliased to addresses 0x2804, 0x2904, 0x2A04 and 0x2B04, respectively.
8.10.6 Receive Descriptor Ring Length - RDLEN (0xC008 + 0x40*n
[n=0...3]; R/W)
This register sets the number of bytes allocated for descriptors in the circular descriptor buffer. It must
be 128-byte aligned.
Reserved_1 16 1b
Reserved.
Write 1b, ignore on read.
PSR_type17 17 1b Header includes MAC, (VLAN/SNAP) IPv6, TCP, NFS only.
PSR_type18 18 1b Header includes MAC, (VLAN/SNAP) IPv6, UDP, NFS only.
Reserved 31:19 0x0
Reserved.
Write 0b, ignore on read.
Field
1
1. Software should program the RDBAL[n] register only when a queue is disabled (RXDCTL[n].Enable = 0b).
Bit(s) Initial Value Description
Lower_0 6:0 0x0
Ignored on writes.
Returns 0x0 on reads.
RDBAL 31:7 X Receive Descriptor Base Address Low.
Field
1
1. Software should program the RDBAH[n] register only when a queue is disabled (RXDCTL[n].Enable = 0b).
Bit(s) Initial Value Description
RDBAH 31:0 X Receive Descriptor Base Address [63:32].
Field Bit(s) Initial Value Description