Data Sheet

Ethernet Controller I210 — Programming Interface
434
8.10 Receive Register Descriptions
8.10.1 Receive Control Register - RCTL (0x0100; R/W)
Field Bit(s) Initial Value Description
Reserved 0 0b
Reserved.
Write 0b, ignore on read.
RXEN 1 0b
Receiver Enable.
The receiver is enabled when this bit is set to 1b. Writing this bit to 0b stops reception
after receipt of any in progress packet. All subsequent packets are then immediately
dropped until this bit is set to 1b.
SBP 2 0b
Store Bad Packets
0b = Do not store.
1b = Store bad packets.
This bit controls the MAC receive behavior. A packet is required to pass the address
(or normal) filtering before the SBP bit becomes effective. If SBP = 0b, then all
packets with layer 1 or 2 errors are rejected. The appropriate statistic would be
incremented. If SBP = 1b, then these packets are received (and transferred to host
memory). The receive descriptor error field (RDESC.ERRORS) should have the
corresponding bit(s) set to signal the software device driver that the packet is erred.
In some operating systems the software device driver passes this information to the
protocol stack. In either case, if a packet only has layer 3+ errors, such as IP or TCP
checksum errors, and passes other filters, the packet is always received (layer 3+
errors are not used as a packet filter).
Note: Symbol errors before the SFD are ignored. Any packet must have a valid SFD
(RX_DV with no RX_ER in 10/100/1000BASE-T mode) in order to be
recognized by the I210 (even bad packets). Also, erred packets are not
routed to the MNG even if this bit is set.
UPE 3 0b
Unicast Promiscuous Enabled.
0b = Disabled.
1b = Enabled.
MPE 4 0b
Multicast Promiscuous Enabled.
0b = Disabled.
1b = Enabled.
LPE 5 0b
Long Packet Reception Enable.
0b = Disabled.
1b = Enabled.
LPE controls whether long packet reception is permitted. If LPE is 0b,hardware
discards long packets over 1518, 1522 or 1526 bytes depending on the
CTRL_EXT.EXT_VLAN bit and the detection of a VLAN tag in the packet. If LPE is
1b,the maximum packet size that the I210 can receive is defined in the RLPML.RLPML
register.
LBM 7:6 00b
Loopback Mode.
Controls the loopback mode of the I210.
00b = Normal operation (or PHY loopback in 10/100/1000BASE-T mode).
01b = MAC loopback (test mode).
10b = Undefined.
11b = Loopback via internal SerDes (SerDes/SGMII/KX mode only).
When using the internal PHY, LBM should remain set to 00b and the PHY instead
configured for loopback through the MDIO interface.
Note: PHY devices require programming for loopback operation using MDIO
accesses.
Reserved 11:8 0x0
Reserved.
Write 0x0, ignore on read.