Data Sheet

Programming Interface — Ethernet Controller I210
433
8.9.3 MSI-X Table Entry Message - MSIXTMSG (BAR3: 0x0008 +
0x10*n [n=0...4]; R/W)
8.9.4 MSI-X Table Entry Vector Control - MSIXTVCTRL (BAR3: 0x000C
+ 0x10*n [n=0...4]; R/W)
8.9.5 MSIXPBA Bit Description – MSIXPBA (BAR3: 0x2000; RO)
8.9.6 MSI-X PBA Clear – PBACL (0x5B68; R/W1C)
Field Bit(s) Initial Value Description
Message
Data
31:0 0x0
System-Specific Message Data.
For MSI-X messages, the contents of this field from an MSI-X table entry
specifies the data written during the memory write transaction.
In contrast to message data used for MSI messages, the low-order
message data bits in MSI-X messages are not modified by the function.
Field Bit(s) Initial Value Description
Mask 0 1b
When this bit is set, the function is prohibited from sending a message
using this MSI-X table entry. However, any other MSI-X table entries
programmed with the same vector are still capable of sending an equivalent
message unless they are also masked.
Reserved 31:1 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
Pending Bits 4:0 0x0
For each pending bit that is set, the function has a pending message for
the associated MSI-X table entry.
Pending bits that have no associated MSI-X table entry are reserved.
Reserved 31:5 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
PENBITCLR 4:0 0x0
MSI-X Pending bits Clear.
Writing a 1b to any bit clears the corresponding MSIXPBA bit; writing a 0b
has no effect.
Note: Bits are set for a single PCIe clock cycle and then cleared.
Reserved 31:5 0x0
Reserved.
Write 0x0, ignore on read.