Data Sheet

Ethernet Controller I210 — Programming Interface
432
The pending bit array register indicates which vectors have pending interrupts. The structure is listed in
Table 8-22.
Note: N = 5.
Note: N = 5. As a result, only Qword0 is implemented.
8.9.1 MSI-X Table Entry Lower Address - MSIXTADD (BAR3: 0x0000 +
0x10*n [n=0...4]; R/W)
8.9.2 MSI-X Table Entry Upper Address - MSIXTUADD (BAR3: 0x0004 +
0x10*n [n=0...4]; R/W)
Table 8-22. MSI-X Table Structure
DWORD3
MSIXTVCTRL
DWORD2
MSIXTMSG
DWORD1
MSIXTUADD
DWORD0
MSIXTADD
Entry
Number
BAR 3 - Offset
Vector Control Msg Data Msg Upper Addr Msg Addr Entry 0 Base (0x0000)
Vector Control Msg Data Msg Upper Addr Msg Addr Entry 1 Base + 1*16
Vector Control Msg Data Msg Upper Addr Msg Addr Entry 2 Base + 2*16
... ... ... ... ... ...
Vector Control Msg Data Msg Upper Addr Msg Addr Entry (N-1) Base + (N-1) *16
Table 8-23. MSI-X PBA Structure
MSIXPBA[63:0] Qword
Number
BAR 3 - Offset
Pending Bits 0 through 63 QWORD0 Base (0x2000)
Pending Bits 64 through 127 QWORD1 Base+1*8
... ... ...
Pending Bits ((N-1) div 64)*64 through N-1 QWORD((N-1) div 64) BASE + ((N-1) div 64)*8
Field Bit(s) Initial Value Description
Message
Address LSB
(RO)
1:0 0x0
For proper Dword alignment, software must always write 0b’s to these
two bits. Otherwise, the result is undefined.
Message
Address
31:2 0x0
System-Specific Message Lower Address.
For MSI-X messages, the contents of this field from an MSI-X table entry
specifies the lower portion of the Dword-aligned address for the memory
write transaction.
Field Bit(s) Initial Value Description
Message
Address
31:0 0x0 System-Specific Message Upper Address.