Data Sheet

Interconnects—Ethernet Controller I210
43
Figure 3-2. MCTP over PCIe VDM Header Format
3.1.4.4 Ordering Rules
The I210 meets the PCIe ordering rules (PCI-X rules) by following the PCI simple device model:
• Deadlock avoidance - Master and target accesses are independent. The response to a target access
does not depend on the status of a master request to the bus. If master requests are blocked, such
as due to no credits, target completions might still proceed (if credits are available).
• Descriptor/data ordering - The I210 does not proceed with some internal actions until respective
data writes have ended on the PCIe link:
— The I210 does not update an internal header pointer until the descriptors that the header
pointer relates to are written to the PCIe link.
— The I210 does not issue a descriptor write until the data that the descriptor relates to is written
to the PCIe link.
The I210 might issue the following master read request from each of the following clients:
• One Rx Descriptor Read
• One Tx Descriptor Read
• Tx Data Read (up to 6)
Completing separate read requests are not guaranteed to return in order. Completions for a single read
request are guaranteed to return in address order.
3.1.4.4.1 Out of Order Completion Handling
In a split transaction protocol, when using multiple read requests in a multi processor environment,
there is a risk that completions arrive from the host memory out of order and interleaved. In this case,
the I210 sorts the request completions and transfers them to the Ethernet in the correct order.
+0 +1 +2 +3
76543210765432107654321076543210
FMT
011
Type
10r2r1r0
R
TC
000
R
A
tt
r
R
T
H
T
D
E
P
Attr
[1:0]
AT
00
Length
00_000x_xxxx
PCI Requester ID
PCI Tag Field
Message Code
Vendor Defined = 0111_1111b
R
Pad
Len
MCTP VDM
code - 0000b
PCI Target ID (For Route by ID messages,
otherwise = Reserved)
Vendor ID = 0x1AB4 (DMTF)