Data Sheet

Programming Interface — Ethernet Controller I210
431
8.8.17 General Purpose Interrupt Enable - GPIE (0x1514; RW)
8.9 MSI-X Table Register Descriptions
These registers are used to configure the MSI-X mechanism. The Message Address and Message Upper
Address registers set the address for each of the vectors. The message register sets the data sent to
the relevant address. The vector control registers are used to enable specific vectors.
INT_Alloc[9] 10:8 0x0
Defines the MSI-X vector assigned to the Other Cause interrupt.
Valid values are 0 to 4.
Reserved 14:11 0x0
Reserved.
Write 0x0, ignore on read.
INT_Alloc[9] 15 0b Valid bit for INT_Alloc[9].
Reserved 31:16 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
NSICR 0 0b
Non Selective Interrupt Clear on Read.
When set, every read of ICR clears it. When this bit is cleared, an ICR read
causes it to be cleared only if an actual interrupt was asserted or IMS =
0x0.
Refer to Section 7.3.3 for additional information.
Reserved 3:1 0x0
Reserved.
Write 0x0, ignore on read.
Multiple MSIX 4 0b
0b = In MSI or MSI-X mode, with a single vector, IVAR maps Rx/Tx causes
to 4 EICR bits but MSIX[0] is asserted for all.
1b = MSIX mode, IVAR maps Rx/Tx causes, TCP Timer and Other Cause
interrupts to 5 MSI-x vectors reflected in 5 EICR bits.
Note: When set, the EICR register is not cleared on read.
Reserved 6:5 0x0
Reserved.
Write 0x0, ignore on read.
LL Interval 11:7 0x0
Low Latency Credits Increment Rate.
The interval is specified in 4 s increments.
Note: When LLI moderation is enabled (LLI_EN bit set), this filed shall
be set with a value different than 0x0.
Reserved 29:12 0x0
Reserved.
Write 0x0, ignore on read.
EIAME 30 0b
Extended Interrupt Auto Mask Enable.
When set (usually in MSI-X mode) and after sending a MSI-X message, if
bits in the EIAM register associated with this message are set, then the
corresponding bits in the EIMS register are cleared. Otherwise, EIAM is
used only after reading or writing the EICR/EICS registers.
Note: When this bit is set in MSI mode, setting of any bit in the EIAM
register causes the clearing of all bits in the EIMS register and
masking of all interrupts after generating a MSI interrupt.
PBA_support 31 0b
PBA Support.
When set, setting one of the extended interrupts masks via EIMS causes
the PBA bit of the associated MSI-X vector to be cleared. Otherwise, the
I210 behaves in a way that supports legacy INT-x interrupts.
Note: Should be cleared when working in INT-x or MSI mode and set in
MSI-X mode.
Field Bit(s) Initial Value Description