Data Sheet

Ethernet Controller I210 — Programming Interface
430
8.8.15 Interrupt Vector Allocation Registers - IVAR (0x1700 + 4*n
[n=0...1]; RW)
These registers have two modes of operation:
1. In MSI-X mode, these registers define the allocation of the different interrupt causes as defined in
Table 7-50 to one of the MSI-X vectors. Each INT_Alloc[i] (i=0...7) field is a byte indexing an entry
in the MSI-X Table Structure and MSI-X PBA Structure.
2. In non MSI-X mode, these registers define the allocation of the Rx and Tx queues interrupt causes
to one of the RxTxQ bits in the EICR register. Each INT_Alloc[i] (i=...7) field is a byte indexing the
appropriate RxTxQ bit as defined in Table 7-49
.
Note: If invalid values are written to the INT_Alloc fields the result is unexpected.
8.8.16 Interrupt Vector Allocation Registers - MISC IVAR_MISC
(0x1740; RW)
This register is used only in MSI-X mode. This register defines the allocation of the Other Cause and
TCP Timer interrupts to one of the MSI-X vectors.
Field Bit(s) Initial Value Description
INT_Alloc[4*n] 2:0 0x0
Defines the MSI-X vector assigned to Rx0 or Rx2 for IVAR[0] or IVAR[1],
respectively. Valid values are 0 to 4 for MSI-X mode and 0 to 3 in non-MSI-X mode.
Reserved 6:3 0x0
Reserved.
Write 0x0, ignore on read.
INT_Alloc[4*n] 7 0b Valid bit for INT_Alloc[4*n].
INT_Alloc[4*n+1] 10:8 0x0
Defines the MSI-X vector assigned to Tx0 or Tx2 for IVAR[0] or IVAR[1],
respectively. Valid values are 0 to 4 for MSI-X mode and 0 to 3 in non-MSI-X mode.
Reserved 14:11 0x0
Reserved.
Write 0x0, ignore on read.
INT_Alloc[4*n+1] 15 0b Valid bit for INT_Alloc[4*n+1].
INT_Alloc[4*n+2] 18:16 0x0
Defines the MSI-X vector assigned to Rx1 or Rx3 for IVAR[0] or IVAR[1],
respectively. Valid values are 0 to 4 for MSI-X mode and 0 to 3 in non-MSI-X mode.
Reserved 22:19 0x0
Reserved.
Write 0x0, ignore on read.
INT_Alloc[4*n+2] 23 0b Valid bit for INT_Alloc[4*n+2].
INT_Alloc[4*n+3] 26:24 0x0
Defines the MSI-X vector assigned to Tx1 or Tx3 for IVAR[0] or IVAR[1],
respectively. Valid values are 0 to 4 for MSI-X mode and 0 to 3 in non-MSI-X mode.
Reserved 30:27 0x0
Reserved.
Write 0x0, ignore on read.
INT_Alloc[4*n+3] 31 0b Valid bit for INT_Alloc[4*n+3].
Field Bit(s) Initial Value Description
INT_Alloc[8] 2:0 0x0
Defines the MSI-X vector assigned to the TCP timer interrupt
cause. Valid values are 0 to 4.
Reserved 6:3 0x0
Reserved.
Write 0x0, ignore on read.
INT_Alloc[8] 7 0b Valid bit for INT_Alloc[8].