Data Sheet

Programming Interface — Ethernet Controller I210
429
8.8.14 Interrupt Throttle - EITR (0x1680 + 4*n [n = 0...4]; R/W)
Each EITR is responsible for an interrupt cause (RxTxQ, TCP timer and Other Cause). The allocation of
EITR-to-interrupt cause is through the IVAR registers.
Software uses this register to pace (or even out) the delivery of interrupts to the host processor. This
register provides a guaranteed inter-interrupt delay between interrupts asserted by the I210,
regardless of network traffic conditions. To independently validate configuration settings, software can
use the following algorithm to convert the inter-interrupt interval value to the common interrupts/sec.
performance metric:
interrupts/sec = (1 * 10
-6
sec x interval)
-1
A counter counts in units of 1*10
-6
sec. After counting interval number of units, an interrupt is sent to
the software. The previous equation gives the number of interrupts per second. The equation that
follows is the time in seconds between consecutive interrupts.
For example, if the interval is programmed to 125 (decimal), the I210 guarantees the processor does
not receive an interrupt for 125 s from the last interrupt. The maximum observable interrupt rate from
the I210 should never exceed 8000 interrupts/sec.
Inversely, inter-interrupt interval value can be calculated as:
inter-interrupt interval = (1 * 10
-6
sec x interrupt/sec)
-1
The optimum performance setting for this register is very system and configuration specific. An initial
suggested range is 2 to 175 (0x02 to 0xAF).
Note: Setting EITR to a non-zero value can cause an interrupt cause Rx/Tx statistics miscount.
Note: The EITR register and interrupt mechanism is not reset by device reset (CTRL.DEV_RST).
Occurrence of device reset interrupt causes immediate generation of all pending interrupts.
Field Bit(s) Initial Value Description
Reserved 1:0 0x0
Reserved.
Write 0x0, ignore on read.
Interval 14:2 0x0
Minimum Inter-interrupt Interval.
The interval is specified in 1 s increments.
A null value is not a valid setting.
LLI_EN 15 0b LLI moderation enable.
LL Counter
(RWM)
20:16 0x0
Reflects the current credits for that EITR for LL interrupts. If the CNT_INGR is not set,
this counter can be directly written by software at any time to alter the throttles
performance
Moderation
Counter
(RWM)
30:21 0x0
Down counter, exposes only the 10 most significant bits of the real 12-bit counter.
Loaded with interval value each time the associated interrupt is signaled. Counts
down to zero and stops. The associated interrupt is signaled each time this counter is
zero and an associated (via the Interrupt Select register) EICR bit is set.
If the CNT_INGR is not set, this counter can be directly written by software at any
time to alter the throttles performance.
CNT_INGR
(WO)
31 0b
When set, hardware does not override the counters fields (ITR counter and LLI credit
counter), so they keep their previous value.
Relevant for the current write only and is always read as zero.