Data Sheet

Ethernet Controller I210 — Programming Interface
428
8.8.13 Interrupt Acknowledge Auto Mask Register - IAM (0x1510; R/W)
RXDMT0 4 0b Clears the mask for Receive Descriptor Minimum Threshold Hit interrupt.
Reserved 5 0b
Reserved.
Write 0b, ignore on read.
Rx Miss 6 0b Clears the mask for the Rx Miss interrupt.
RXDW 7 0b Clears the mask for the Receiver Descriptor Write Back interrupt.
Reserved 9:8 0b
Reserved.
Write 0b, ignore on read.
GPHY 10 0b Clears the mask for the Internal 1000/100/10BASE-T PHY interrupt.
GPI_SDP0 11 0b Clears the mask for the General Purpose interrupt, related to SDP0 pin.
GPI_SDP1 12 0b Clears the mask for the General Purpose interrupt, related to SDP1 pin.
GPI_SDP2 13 0b Clears the mask for the General Purpose interrupt, related to SDP2 pin.
GPI_SDP3 14 0b Clears the mask for the General Purpose interrupt, related to SDP3 pin.
Reserved 17:15 0x0
Reserved.
Write 0x0, ignore on read.
MNG 18 0b Clears the mask for the Management Event interrupt.
Time_Sync 19 0b Clears the mask for the Time_Sync interrupt.
Reserved 20 0b
Reserved.
Write 0b, ignore on read.
Reserved 21 0b
Reserved.
Write 0b, ignore on read.
FER 22 0b Clears the mask for the Fatal Error interrupt.
Reserved 23 0b
Reserved.
Write 0b, ignore on read.
PCI Exception 24 0b Clears the mask for the PCI Exception interrupt.
SCE 25 0b Clears the mask for the DMA Coalescing Clock Control Event interrupt.
Software WD 26 0b Clears the mask for Software Watchdog Interrupt.
Reserved 28:27 0b
Reserved.
Write 0b, ignore on read.
TCP timer 29 0b Clears the mask for TCP timer interrupt.
DRSTA 30 0b Clears the mask for Device Reset Asserted interrupt.
Reserved 31 0b
Reserved.
Write 0b, ignore on read.
Field Bit(s) Initial Value Description
IAM_VALUE 30:0 0x0
An ICR read or write has the side effect of writing the contents of this
register to the IMC register. If GPIE.NSICR = 0b, then the copy of this
register to the IMC register occurs only if at least one bit is set in the IMS
register and there is a true interrupt as reflected in the ICR.INTA bit.
Refer to Section 7.3.3 for additional information.
Note: Note: Bit 30 of this register is not reset by device reset
(CTRL.DEV_RST).
Reserved 31 0b
Reserved.
Write 0b, ignore on read.
Field Bit(s) Initial Value Description