Data Sheet

Programming Interface — Ethernet Controller I210
427
8.8.12 Interrupt Mask Clear Register - IMC (0x150C; WO)
Software uses this register to disable an interrupt. Interrupts are presented to the bus interface only
when the mask bit is set to 1b and the cause bit set to 1b. The status of the mask bit is reflected in the
Interrupt Mask Set/Read register (refer to Section 8.8.11), and the status of the cause bit is reflected in
the Interrupt Cause Read register (refer to Section 8.8.9). Reading this register returns the value of the
IMS register.
Software blocks interrupts by clearing the corresponding mask bit. This is accomplished by writing a 1b
to the corresponding bit in this register. Bits written with 0b are unchanged (their mask status does not
change).
Software device driver should set all the bits in this register related to the current interrupt request
when handling interrupts, even though the interrupt was triggered by part of the causes that were
allocated to this vector. Refer to Section 7.3.3 for additional information.
GPI_SDP1 12 0b Sets/Reads the mask for General Purpose Interrupt, related to SDP1 pin.
GPI_SDP2 13 0b Sets/Reads the mask for General Purpose Interrupt, related to SDP2 pin.
GPI_SDP3 14 0b Sets/Reads the mask for General Purpose Interrupt, related to SDP3 pin.
Reserved 17:15 0x0
Reserved.
Write 0x0, ignore on read.
MNG 18 0b Sets/reads the mask for Management Event interrupt.
Time_Sync 19 0b Sets/reads the mask for Time_Sync interrupt.
Reserved 20 0b
Reserved.
Write 0b, ignore on read.
Reserved 21 0b
Reserved.
Write 0b, ignore on read.
FER 22 0b Sets/reads the mask for the Fatal Error interrupt.
Reserved 23 0b
Reserved.
Write 0b, ignore on read.
PCI Exception 24 0b Sets/reads the mask for the PCI Exception interrupt.
SCE 25 0b Sets/reads the mask for the DMA Coalescing Clock Control Event interrupt.
Software WD 26 0b Sets/reads the mask for the Software Watchdog interrupt.
Reserved 28 0b
Reserved.
Write 0b, ignore on read.
TCP Timer 29 0b Sets/reads the mask for TCP timer interrupt.
DRSTA 30 0b
Sets/reads the mask for Device Reset Asserted interrupt.
Note: Bit is not reset by device reset (CTRL.DEV_RST).
Reserved 31 0b
Reserved.
Write 0b, ignore on read.
Field Bit(s) Initial Value Description
TXDW 0 0b Clears the mask for Transmit Descriptor Written Back interrupt.
Reserved 1 0b
Reserved.
Write 0b, ignore on read.
LSC 2 0b Clears the mask for Link Status Change interrupt.
Reserved 3 0b
Reserved.
Write 0b, ignore on read.
Field Bit(s) Initial Value Description