Data Sheet

Ethernet Controller I210 — Programming Interface
426
8.8.11 Interrupt Mask Set/Read Register - IMS (0x1508; R/W)
Reading this register returns bits that have an interrupt mask set. An interrupt is enabled if its
corresponding mask bit is set to 1b and disabled if its corresponding mask bit is set to 0b. A PCIe
interrupt is generated each time one of the bits in this register is set and the corresponding interrupt
condition occurs. The occurrence of an interrupt condition is reflected by having a bit set in the
Interrupt Cause Read register (refer to Section 8.8.9).
A particular interrupt can be enabled by writing a 1b to the corresponding mask bit in this register. Any
bits written with a 0b are unchanged. As a result, if software desires to disable a particular interrupt
condition that had been previously enabled, it must write to the Interrupt Mask Clear Register (refer to
Section 8.8.12) rather than writing a 0b to a bit in this register. Refer to Section 7.3.3 for additional
information.
Reserved 21:20 0x0
Reserved.
Write 0x0, ignore on read.
FER 22 0b Sets the Fatal Error interrupt.
Reserved 23 0b
Reserved.
Write 0b, ignore on read.
PCI Exception 24 0b Sets the PCI Exception interrupt.
SCE 25 0b Sets the DMA Coalescing Clock Control Event interrupt.
Software WD 26 0b Sets the Software Watchdog interrupt.
Reserved 27 0b
Reserved.
Write 0b, ignore on read.
Reserved 28 0b Reserved.
TCP Timer 29 0b Sets the TCP timer interrupt.
DRSTA 30 0b
Sets the Device Reset Asserted Interrupt.
Note that when setting this bit a DRSTA interrupt is generated on this port
only.
Reserved 31 0b
Reserved.
Write 0b, ignore on read.
Field Bit(s) Initial Value Description
TXDW 0 0b Sets/reads the mask for Transmit Descriptor Written Back interrupt.
Reserved 1 0b
Reserved.
Write 0b, ignore on read.
LSC 2 0b Sets/Reads the mask for Link Status Change interrupt.
Reserved 3 0b
Reserved.
Write 0b, ignore on read.
RXDMT0 4 0b Sets/reads the mask for Receive Descriptor Minimum Threshold Hit interrupt.
Reserved 5 0b
Reserved.
Write 0b, ignore on read.
Rx Miss 6 0b Sets/reads the mask for the Rx Miss interrupt.
RXDW 7 0b Sets/reads the mask for Receiver Descriptor Write Back interrupt.
Reserved 9:8 0b
Reserved.
Write 0b, ignore on read.
GPHY 10 0b Sets/Reads the mask for Internal 1000/100/10BASE-T PHY interrupt.
GPI_SDP0 11 0b Sets/Reads the mask for General Purpose Interrupt, related to SDP0 pin.
Field Bit(s) Initial Value Description