Data Sheet

Programming Interface — Ethernet Controller I210
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8.8.10 Interrupt Cause Set Register - ICS (0x1504; WO)
Software uses this register to set an interrupt condition. Any bit written with a 1b sets the
corresponding interrupt. This results in the corresponding bit being set in the Interrupt Cause Read
Register (refer to Section 8.8.9). A PCIe interrupt is generated if one of the bits in this register is set
and the corresponding interrupt is enabled through the Interrupt Mask Set/Read Register (refer to
Section 8.8.11). Bits written with 0b are unchanged. Refer to Section 7.3.3 for additional information.
SCE 25 0b
DMA Coalescing Clock Control Event.
This bit is set when the multicast or broadcast DMA coalescing clock control
mechanism is activated or de-activated.
Software WD 26 0b
Software Watchdog.
This bit is set after a software watchdog timer times out.
Reserved 27 0b
Reserved.
Write 0x0, ignore on read.
Reserved 28 0b Reserved.
TCP Timer 29 0b
TCP Timer Interrupt.
Activated when the TCP timer reaches its terminal count.
DRSTA 30 0b
Device Reset Asserted.
Indicates CTRL.DEV_RST was asserted. When a device reset occurs, the port
should re-initialize registers and descriptor rings.
Note: This bit is not reset by device reset (CTRL.DEV_RST).
INTA 31 0b
Interrupt Asserted.
Indicates that the INT line is asserted. Can be used by the software device driver
in a shared interrupt scenario to decide if the received interrupt was emitted by
the I210. This bit is not valid in MSI/MSI-X environments.
Field Bit(s) Initial Value Description
TXDW 0 0b Sets the Transmit Descriptor Written Back Interrupt.
Reserved 1 0b
Reserved.
Write 0b, ignore on read.
LSC 2 0b Sets the Link Status Change Interrupt.
Reserved 3 0b
Reserved.
Write 0x0, ignore on read.
RXDMT0 4 0b Sets the Receive Descriptor Minimum Threshold Hit Interrupt.
Reserved 5 0b
Reserved.
Write 0x0, ignore on read.
Rx Miss 6 0b Sets the Rx Miss Interrupt.
RXDW 7 0b Sets the Receiver Descriptor Write Back Interrupt.
Reserved 9:8 0b
Reserved.
Write 0b, ignore on read.
GPHY 10 0b Sets the internal 1000/100/10BASE-T PHY interrupt.
GPI_SDP0 11 0b Sets the General Purpose interrupt, related to SDP0 pin.
GPI_SDP1 12 0b Sets the General Purpose interrupt, related to SDP1 pin.
GPI_SDP2 13 0b Sets the General Purpose interrupt, related to SDP2 pin.
GPI_SDP3 14 0b Sets the General Purpose interrupt, related to SDP3 pin.
Reserved 17:15 0x0
Reserved.
Write 0x0, ignore on read.
MNG 18 0b Sets the Management Event Interrupt.
Time_Sync 19 0b Sets the Time_Sync interrupt.
Field Bit(s) Initial Value Description