Data Sheet

Ethernet Controller I210 — Programming Interface
424
RXDMT0 4 0b
Receive Descriptor Minimum Threshold Reached.
Indicates that the minimum number of receive descriptors are available and
software should load more receive descriptors.
Reserved 5 0b
Reserved.
Write 0x0, ignore on read.
Rx Miss 6 0b
Missed packet interrupt is activated for each received packet that overflows the
Rx packet buffer (overrun). Note that the packet is dropped and also increments
the associated MPC counter.
Note: Could be caused by no available receive buffers or because PCIe receive
bandwidth is inadequate.
RXDW 7 0b
Receiver Descriptor Write Back.
Set when the I210 writes back an Rx descriptor to memory.
Reserved 9:8 0b
Reserved.
Write 0x0, ignore on read.
GPHY 10 0b
Internal 1000/100/10BASE-T PHY interrupt.
Refer to Section 8.27 for further information.
GPI_SDP0 11 0b
General Purpose Interrupt on SDP0.
If GPI interrupt detection is enabled on this pin (via CTRL.SDP0_GPIEN), this
interrupt cause is set when the SDP0 is sampled high.
GPI_SDP1 12 0b
General Purpose Interrupt on SDP1.
If GPI interrupt detection is enabled on this pin (via CTRL.SDP1_GPIEN), this
interrupt cause is set when the SDP1 is sampled high.
GPI_SDP2 13 0b
General Purpose Interrupt on SDP2.
If GPI interrupt detection is enabled on this pin (via CTRL_EXT.SDP2_GPIEN),
this interrupt cause is set when the SDP2 is sampled high.
GPI_SDP3 14 0b
General Purpose Interrupt on SDP3.
If GPI interrupt detection is enabled on this pin (via CTRL_EXT.SDP3_GPIEN),
this interrupt cause is set when the SDP3 is sampled high.
Reserved 15 0b Reserved.
Reserved 17:16 00b
Reserved.
Write 0x0, ignore on read.
MNG 18 0b
Manageability Event Detected.
Indicates that a manageability event happened. When bit is set due to detection
of error by management, FWSM.Ext_Err_Ind field is updated with the error
cause.
Time_Sync 19 0b
Time_Sync Interrupt.
This interrupt cause is set if the interrupt is generated by the Time Sync
interrupt (See TSICR and TSIM registers).
Reserved 21:20 0b
Reserved.
Write 0x0, ignore on read.
FER 22 0b
Fatal Error.
This bit is set when a fatal error is detected in one of the memories.
Reserved 23 0b
Reserved.
Write 0x0, ignore on read.
PCI Exception 24 0b
The PCI timeout exception is activated by one of the following events when the
specific PCI event is reported in the PICAUSE register and the appropriate bit in
the PIENA register is set:
1. I/O completion abort.
2. Unsupported I/O request (wrong address).
3. Byte-enable error - Access to the client that does not support partial BE
access (All but Flash, MSIX and the PCIe target).
4. Timeout occurred in the FUNC block.
5. BME of the PF is cleared.
Field Bit(s) Initial Value Description