Data Sheet

Programming Interface — Ethernet Controller I210
423
In MSI-X mode, this register controls which of the bits in the EIMS register to clear upon interrupt
generation if enabled via the GPIE.EIAME bit.
Note: When operating in MSI mode and setting any bit in the EIAM register causes the clearing of all
bits in the EIMS register and the masking of all interrupts after generating a MSI interrupt.
Note: Bits are not reset by device reset (CTRL.DEV_RST).
8.8.9 Interrupt Cause Read Register - ICR (0x1500; RC/W1C)
This register contains the interrupt conditions for the I210 that are not present directly in the EICR.
Each time an ICR interrupt causing event occurs, the corresponding interrupt bit is set in this register.
The EICR.Other bit reflects the setting of interrupt causes from ICR as masked by the Interrupt Mask
Set/Read register. Each time all un-masked causes in ICR are cleared, the EICR.Other bit is also
cleared.
ICR bits are cleared on register read. Clear-on-read can be enabled/disabled through a general
configuration register bit. Refer to Section 7.3.3 for additional information.
Auto clear is not available for the bits in this register.
In order to prevent unwanted Link Status Change (LSC) interrupts during initialization, software should
disable this interrupt until the end of initialization.
Table 8-20. EIAM Register - Non-MSI-X Mode (GPIE.Multiple_MSIX = 0b)
Field Bit(s) Initial Value Description
RxTxQ 3:0 0x0 Auto Mask bit for the corresponding EICR RxTxQ interrupt.
Reserved 29:4 0x0
Reserved.
Write 0x0, ignore on read.
TCP Timer 30 0b Auto Mask bit for the corresponding EICR TCP timer interrupt condition.
Other Cause 31 0b Auto Mask bit for the corresponding EICR other cause interrupt condition.
Table 8-21. EIAM Register - MSI-X Mode (GPIE.Multiple_MSIX = 1b)
Field Bit(s) Initial Value Description
MSIX 4:0 0x0
Auto Mask bit for the corresponding EICR bit of MSI-X vectors 4:0.
Note: Bits are not reset by device reset (CTRL.DEV_RST).
Reserved 31:5 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
TXDW 0 0b
Transmit Descriptor Written Back.
Set when the I210 writes back a Tx descriptor to memory.
Reserved 1 0b
Reserved.
Write 0x0, ignore on read.
LSC 2 0b
Link Status Change.
This bit is set each time the link status changes (either from up to down, or from
down to up). This bit is affected by the LINK indication from the PHY (internal
PHY mode).
Reserved 3 0b
Reserved.
Write 0x0, ignore on read.