Data Sheet

Ethernet Controller I210 — Programming Interface
422
Software blocks interrupts by clearing the corresponding mask bit. This is accomplished by writing a 1b
to the corresponding bit location (as defined in the EICR register) of that interrupt in this register. Bits
written with 0b are unchanged (their mask status does not change).
8.8.7 Extended Interrupt Auto Clear - EIAC (0x152C; R/W)
This register is mapped like the EICS, EIMS, and EIMC registers, with each bit mapped to the
corresponding MSI-X vector.
This register is relevant to MSI-X mode only, where read-to-clear can not be used, as it might erase
causes tied to other vectors. If any bits are set in EIAC, the EICR register should not be read. Bits
without auto clear set, need to be cleared with write-to-clear.
Note: EICR bits that have auto clear set are cleared by the internal emission of the corresponding
MSI-X message even if this vector is disabled by the operating system.
The MSI-X message can be delayed by EITR moderation from the time the EICR bit is
activated.
Table 8-19. EIAC Register
8.8.8 Extended Interrupt Auto Mask Enable - EIAM (0x1530; R/W)
Each bit in this register enables clearing of the corresponding bit in EIMS register following read- or
write-to-clear to EICR or setting of the corresponding bit in EIMS following a write-to-set to EICS.
Table 8-17. EIMC Register - Non-MSI-X Mode (GPIE.Multiple_MSIX = 0b)
Field Bit(s) Initial Value Description
RxTxQ 3:0 0x0 Clear the Mask bit for the corresponding EICR RxTXQ interrupt.
Reserved 29:4 0x0
Reserved.
Write 0x0, ignore on read.
TCP Timer 30 0b Clear the Mask bit for the corresponding EICR TCP timer interrupt.
Other Cause 31 1b Clear the Mask bit for the corresponding EICR other cause interrupt.
Table 8-18. EIMC Register - MSI-X Mode (GPIE.Multiple_MSIX = 1b)
Field Bit(s) Initial Value Description
MSI-X 4:0 0x0 Clear the Mask bit for the corresponding EICR bit of MSI-X vectors 4:0.
Reserved 31:5 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
MSI-X 4:0 0x0
Auto clear bit for the corresponding EICR bit of the MSI-X vectors 4:0.
Notes:
• Bits are not reset by device reset (CTRL.DEV_RST).
•When GPIE.Multiple_MSIX = 0b (Non-MSI-X Mode) bits 8 and 9 are read only and
should be ignored.
Reserved 31:5 0x0
Reserved.
Write 0x0, ignore on read.