Data Sheet

Programming Interface — Ethernet Controller I210
421
8.8.5 Extended Interrupt Mask Set/Read - EIMS (0x1524; RWM)
Reading this register returns which bits that have an interrupt mask set. An interrupt in EICR is enabled
if its corresponding mask bit is set to 1b and disabled if its corresponding mask bit is set to 0b. A PCI
interrupt is generated each time one of the bits in this register is set and the corresponding interrupt
condition occurs (subject to throttling). The occurrence of an interrupt condition is reflected by having a
bit set in the Extended Interrupt Cause Read register.
An interrupt might be enabled by writing a 1b to the corresponding mask bit location (as defined in the
EICR register) in this register. Any bits written with a 0b are unchanged. As a result, if software needs
to disable an interrupt condition that had been previously enabled, it must write to the Extended
Interrupt Mask Clear register rather than writing a 0b to a bit in this register.
Note: Bits are not reset by device reset (CTRL.DEV_RST).
8.8.6 Extended Interrupt Mask Clear - EIMC (0x1528; WO)
This register provides software a way to disable certain or all interrupts. Software disables a given
interrupt by writing a 1b to the corresponding bit in this register.
On interrupt handling, the software device driver should set all the bits in this register related to the
current interrupt request even though the interrupt was triggered by part of the causes that were
allocated to this vector.
Interrupts are presented to the bus interface only when the mask bit is set to 1b and the cause bit is set
to 1b. The status of the mask bit is reflected in the Extended Interrupt Mask Set/Read register and the
status of the cause bit is reflected in the Interrupt Cause Read register.
Table 8-14. EICS Register - MSI-X Mode (GPIE.Multiple_MSIX = 1b)
Field Bit(s) Initial Value Description
MSI-X 4:0 0x0 Sets the corresponding EICR bit of MSI-X vectors 4:0
Reserved 31:5 0x0
Reserved.
Write 0x0, ignore on read.
Table 8-15. EIMS Register - Non-MSI-X Mode (GPIE.Multiple_MSIX = 0b)
Field Bit(s) Initial Value Description
RxTxQ 3:0 0x0 Set the Mask bit for the corresponding EICR RxTXQ interrupt.
Reserved 29:4 0x0
Reserved.
Write 0x0, ignore on read.
TCP Timer 30 0b Set the Mask bit for the corresponding EICR TCP timer interrupt condition.
Other Cause 31 1b Set the Mask bit for the corresponding EICR other cause interrupt condition.
Table 8-16. EIMS Register - MSI-X Mode (GPIE.Multiple_MSIX = 1b)
Field Bit(s) Initial Value Description
MSI-X 4:0 0x0
Set the Mask bit for the corresponding EICR bit of the MSI-X vectors 4:0.
Note: Bits are not reset by device reset (CTRL.DEV_RST).
Reserved 31:5 0x0
Reserved
Write 0x0, ignore on read.