Data Sheet

Ethernet Controller I210 — Programming Interface
420
Auto clear can be enabled for any or all of the bits in this register.
Note: Bits are not reset by device reset (CTRL.DEV_RST).
8.8.4 Extended Interrupt Cause Set - EICS (0x1520; WO)
Software uses this register to set an interrupt condition. Any bit written with a 1b sets the
corresponding bit in the Extended Interrupt Cause Read register. An interrupt is then generated if one
of the bits in this register is set and the corresponding interrupt is enabled via the Extended Interrupt
Mask Set/Read register. Bits written with 0b are unchanged.
Note: In order to set bit 31 of the EICR (Other Causes), the ICS and IMS registers should be used in
order to enable one of the legacy causes.
Table 8-11. EICR Register - Non-MSI-X Mode (GPIE.Multiple_MSIX = 0b)
Field Bit(s) Initial Value Description
RxTxQ 3:0 0x0
Receive/Transmit Queue Interrupts.
One bit per queue or a bundle of queues, activated on receive/transmit queue events
for the corresponding bit, such as:
• Receive descriptor write back
• Receive descriptor minimum threshold hit
• Transmit descriptor write back.
The mapping of the actual queue to the appropriate RxTxQ bit is according to the IVAR
registers.
Reserved 29:4 0x0
Reserved.
Write 0x0, ignore on read.
TCP Timer 30 0b
TCP Timer Expired.
Activated when the TCP timer reaches its terminal count.
Other Cause 31 0b
Interrupt Cause Active.
Activated when any bit in the ICR register is set.
Table 8-12. EICR Register - MSI-X Mode (GPIE.Multiple_MSIX = 1b)
Field Bit(s) Initial Value Description
MSIX 4:0 0x0
Indicates an interrupt cause mapped to MSI-X vectors 4:0.
Note: Bits are not reset by device reset (CTRL.DEV_RST).
Reserved 31:5 0x0
Reserved.
Write 0x0, ignore on read.
Table 8-13. EICS Register - Non MSI-X mode (GPIE.Multiple_MSIX = 0b)
Field Bit(s) Initial Value Description
RxTxQ 3:0 0x0 Sets to corresponding EICR RxTXQ interrupt condition.
Reserved 29:4 0x0
Reserved.
Write 0x0, ignore on read.
TCP Timer 30 0b Sets the corresponding EICR TCP timer interrupt condition.
Reserved 31 0b
Reserved.
Write 0b, ignore on read.