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Data Sheet

ManualsBrandsIntel ManualsComputing & OfficeIntel Intel Ethernet Server Adapter I210-T1 - Network adapter 1 Gbps LAN (10/100/1000 Mbps), PCI-Express
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Programming Interface — Ethernet Controller I210
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8.8 Interrupt Register Descriptions
8.8.1 PCIe Interrupt Cause - PICAUSE (0x5B88; RW1/C)
8.8.2 PCIe Interrupt Enable - PIENA (0x5B8C; R/W)
8.8.3 Extended Interrupt Cause - EICR (0x1580; RC/W1C)
This register contains the frequent interrupt conditions for the I210. Each time an interrupt causing
event occurs, the corresponding interrupt bit is set in this register. An interrupt is generated each time
one of the bits in this register is set and the corresponding interrupt is enabled via the Interrupt Mask
Set/Read register. The interrupt might be delayed by the selected Interrupt Throttling register.
Note that the software device driver cannot determine from the RxTxQ bits what was the cause of the
interrupt. The possible causes for asserting these bits are: Receive descriptor write back, receive
descriptor minimum threshold hit, low latency interrupt for Rx, and transmit descriptor write back.
Writing a 1b to any bit in the register clears that bit. Writing a 0b to any bit has no effect on that bit.
Register bits are cleared on register read if GPIE.Multiple_MSIX = 0b.
Field Bit(s) Init. Description
CA 0 0b PCI Completion Abort Exception Issued.
UA 1 0b
Reserved.
Write 0x0, ignore on read.
BE 2 0b Wrong byte-enable exception in the FUNC unit.
TO 3 0b PCI timeout exception in the FUNC unit.
BMEF 4 0b Asserted when Bus-Master-Enable (BME) of the PF is de-asserted.
ABR 5 0b
PCI Completer Abort Received.
PCI Completer Abort (CA) or Unsupported Request (UR) received (set after receiving CA or
UR).
Note: When this bit is set, all PCIe master activity is stopped. Software should issue a
software (CTRL.RST) reset to enable PCIe activity.
Reserved 31:6 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Init. Description
CA 0 0b When set to 1b, the PCI completion abort interrupt is enabled.
UA 1 0b
Reserved.
Write 0x0, ignore on read.
BE 2 0b When set to 1b, the wrong byte-enable interrupt is enabled.
TO 3 0b When set to 1b, the PCI timeout interrupt is enabled.
BMEF 4 0b When set to 1b, the BME interrupt is enabled.
ABR 5 0b When set to 1b, the PCI completion abort received interrupt is enabled.
Reserved 31:6 0x0
Reserved.
Write 0x0, ignore on read.