Data Sheet

Ethernet Controller I210 — Programming Interface
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8.7.3 Software–Firmware Synchronization - SW_FW_SYNC (0x5B5C;
RWM)
This register is intended to synchronize between software and firmware.
Note: If software takes ownership of bits in the SW_FW_SYNC register for a duration longer than 1
second, firmware can take ownership of the bit.
Reset conditions:
— The software-controlled bits 15:0 are reset as any other CSR on global resets, D3hot exit and
Forced TCO. Software is expected to clear the bits on entry to D3 state.
— The firmware controlled bits (bits 31:16) are reset on LAN_PWR_GOOD (power up) and firmware
reset.
Field Bit(s)
Initial
Value
Description
SW_FLASH_SM 0 0b When set to 1b, Flash access is owned by software.
SW_PHY_SM 1 0b When set to 1b, SerDes/PHY access is owned by software.
SW_I2C_SM 2 0b When set to 1b, I
2
C access register set (I2CCMD) is owned by software.
SW_MAC_CSR_SM 3 0b When set to 1b, software owns access to shared CSRs.
Reserved 6:4 0x0
Reserved.
Write 0x0, ignore on read.
SW_SVR_SM 7 0b
When set to 1b, the SVR/LVR control registers are owned by the software device
driver.
SW_MB_SM 8 0b
When Set to 1b, the SWMBWR mailbox write register, is owned by the software
device driver.
Reserved 9 0b
Reserved.
Write 0b, ignore on read.
SW_MNG_SM 10 0b
When set to 1b, the management host interface is owned by the port driver.
This bit can be used by the port driver when updating teaming or proxying
information.
Reserved 15:11 0x0
Reserved.
Write 0x0, ignore on read.
FW_FLASH_SM 16 0b When set to 1b, Flash access is owned by firmware.
FW_PHY_SM 17 0b When set to 1b, PHY access is owned by firmware.
FW_I2C_SM 18 0b When set to 1b, I
2
C access register set (I2CCMD) is owned by firmware.
FW_MAC_CSR_SM 19 0b When set to 1b, firmware owns access to shared CSRs.
Reserved 22:20 0b
Reserved.
Write 0x0, ignore on read.
FW_SVR_SM 23 0b When set to 1b, the SVR/LVR control registers are owned by firmware.
Reserved 31:24 0x0
Reserved
Write 0x0, ignore on read.