Data Sheet

Programming Interface — Ethernet Controller I210
417
Notes:
1. This register should be written only by the manageability firmware. The software device driver should only read this register.
2. Firmware ignores the Flash semaphore in operating system hung states.
3. Bits 15:0 are cleared on firmware reset.
Ext_Err_Ind 24:19 0x0
External Error Indication
Firmware writes here the reason that the firmware operation has stopped.
For example, Flash CRC error, etc.
Possible values:
0x00: No Error.
0x01: Flash CRC error in test configuration module.
Reserved.
0x03: Flash CRC error in common firmware parameters module.
0x04: Flash CRC error in pass through.
0x05: Shadow RAM dump fault.
0x06: Bad Flash contents.
0x07: Reserved.
0x08: Flash CRC error in sideband configuration module.
0x09: Flash CRC error in flexible TCO filter configuration module.
0x0A: Flash CRC Error in NC-SI microcode download module.
0x0B: Flash CRC Error in NC-SI configuration module.
0x0C: Flash CRC Error in traffic type parameters module.
0x0D: Flash CRC Error in inventory Flash structure module.
0x0E: Flash CRC Error in PHY configuration structure module.
0x0F to 0x15: Reserved.
0x16: TLB table exceeded.
0x17: DMA load failed.
0x18: Reserved.
0x19: Flash device not supported.
0x1A: Invalid Flash checksum.
0x1B: Unspecified error.
0x1C to 0x1F: Reserved.
0x20: Flash CRC Error in hardware auto-load.
0x21: No manageability (No Flash).
0x22: TCO isolate mode active.
0x23: Management memory parity error.
0x24: Firmware Flash access failure.
0x25: Other management error detected.
0x26 to 0x03F: Reserved
Note: Following an error detection and FWSM.Ext_Err_ind update, the
ICR.MGMT bit is set and an interrupt is sent to the host. However
when values of 0x00 or 0x21 are placed in the FWSM.Ext_Err_ind
field, the ICR.MGMT bit is not set and an interrupt is not
generated.
PCIe_Config_Err_Ind 25 0b
PCIe Configuration Error Indication.
Set to 1b by firmware when it fails to configure the PCIe interface.
Cleared by firmware after successfully configuring the PCIe interface.
PHY_SERDES0_Config_
Err_Ind
26 0b
PHY/SerDes Configuration Error Indication.
Set to 1b by firmware when it fails to configure LAN PHY/SerDes.
Cleared by firmware after successfully configuring LAN PHY/SerDes.
Reserved 30:27 0b
Reserved.
Write 0b, ignore on read.
Factory MAC address
restored
31 0b
This bit is set if internal firmware restored the factory MAC address at
power up or if the factory MAC address and the regular MAC address were
the same.
Field
1
Bit(s)
Initial
Value
Description