Data Sheet

Programming Interface — Ethernet Controller I210
415
8.7 Semaphore Registers
This section contains registers used to coordinate between firmware and software. The usage of these
registers is described in Section 4.6.11.
8.7.1 Software Semaphore - SWSM (0x5B50; R/W)
Field Bit(s)
Initial
Value
Description
Disable ACL 0 0b When set, the ACL check on the PCIe VDMs is disabled.
Reserved 31:1 0x0
Reserved
Write 0x0, ignore on read
Field Bit(s) Initial Value Description
SMBI (RS) 0 0b
Software/Software Semaphore Bit
This bit is set by hardware when this register is read by the software device
driver and cleared when the host driver writes a 0b to it.
The first time this register is read, the value is 0b. In the next read the
value is 1b (hardware mechanism). The value remains 1b until the software
device driver clears it.
This bit can be used as a semaphore between all I210 driver threads.
This bit is cleared on PCIe reset.
SWESMBI 1 0x0
Software/Firmware Semaphore Bit.
This bit should be set only by the software device driver (read only to
firmware). The bit is not set if bit zero in the FWSM register is set.
The software device driver should set this bit and then read it to verify that
it was set. If it was set, it means that the software device driver can access
the SW_FW_SYNC register.
The software device driver should clear this bit after modifying the
SW_FW_SYNC register.
Note:
• If software takes ownership of the SWSM.SWESMBI bit for a duration
longer than 10 ms, Firmware can take ownership of the bit.
• Hardware clears this bit on a PCIe reset.
Reserved 30:2 0x0
Reserved.
Write 0x0, ignore on read.
Reserved 31 0b Reserved.