Data Sheet

Ethernet Controller I210 — Programming Interface
414
8.6.12 PCIe BAR Control - BARCTRL (0x5BFC; R/W) Target
8.6.13 Read Request To Data Completion Delay Register - RR2DCDELAY
(0x5BF4; RC)
Note: Register resets by LAN_PWR_GOOD and PCIe reset.
8.6.14 PCIe MCTP Register - PCIEMCTP (0x5B4C; RO to Host)
Note: Reset by PCIe reset.
Field Bit(s) Initial Value Description
Reserved 31:0 0x0
Reserved
Write 0x0, ignore on read.
Table 8-10. Usable Flash Size and CSR Mapping Window Size
FLBARSize CSRSize Resulted CSR + Flash BAR Size Installed Flash Device Usable Flash Space
000b 0 128 KB No Flash 0
000b 1 256 KB 64 KB 64 KB
001b 0 256 KB 128 KB 128 KB
001b 1 n/a n/a Reserved
010b 0 256 KB 256 KB 256 KB minus 128 KB
010b 1 512 KB 256 KB 256 KB
011b 0 512 KB 512 KB 512 KB minus 128 KB
011b 1 1 MB 512 KB 512 KB
100b 0 1 MB 1 MB 1 MB minus 128 KB
100b 1 2 MB 1 MB 1 MB
101b 0 2 MB 2 MB 2 MB minus 128 KB
101b 1 4 MB 2 MB 2 MB
110b 0 4 MB 4 MB 4 MB minus 128 KB
110b 1 8 MB 4MB 4 MB
111b 0 8 MB 8MB 8 MB minus 128 KB
111b 1 16 MB 8MB 8 MB
Field Bit(s) Initial Value Description
Max Split Time 31:0 0x0
This field captures the maximum PCIe split time in 16 ns units, which is the
maximum delay between the read request to the first data completion. This
is giving an estimation of the PCIe round trip time.