Data Sheet

Programming Interface — Ethernet Controller I210
413
8.6.10 Mirrored Revision ID - MREVID (0x5B64; R/W)
8.6.11 PCIe Control Extended Register - GCR_EXT (0x5B6C; RW)
Field Bit(s) Initial Value Description
Func Power State 1:0 00b
Power state indication of Function.
00b = DR.
01b = D0u.
10b = D0a.
11b = D3.
This field resets only by LAN_PWR_GOOD.
Reserved 2 0b Reserved.
Func Aux_En 3 0b
Function Auxiliary (AUX) Power PM Enable bit shadow from the
configuration space.
Reserved 28:4 0x0
Reserved.
Write 0x0, ignore on read.
MNGCG 29 0b
MNG Clock Gated.
When set, indicates that the manageability clock is gated.
Reserved 30 0b Reserved.
PM State Changed (RC) 31 0b
Indicates that one or more of the functional power states have changed.
This bit is also a signal to the MC to create an interrupt.
This bit is cleared on read by the MC.
This bit resets only by LAN_PWR_GOOD.
Field Bit(s) Initial Value Description
Flash RevID 7:0 0x0
Mirroring of revision ID loaded from the Flash in PCIe configuration space
(from Device Rev ID word, address 0x1E).
Step REV ID 15:8
0x01 for A1
0x03 for A2
Revision ID from FUNC configuration space.
Reserved 31:16 0x0
Reserved
Write 0x0, ignore on read.
Field Bit(s) Init. Description
Reserved 3:0 0x0 Reserved.
APBACD 4 0b
Auto PBA Clear Disable. When set to 1b, software can clear the PBA only by a direct write to
clear access to the PBA bit. When set to 0b, any active PBA entry is cleared on the falling edge
of the appropriate interrupt request to the PCIe block. The appropriate interrupt request is
cleared when software sets the associated Interrupt Mask bit in the EIMS (re-enabling the
interrupt) or by direct write to clear to the PBA.
Reserved 31:5 0x0 Reserved.