Data Sheet

Programming Interface — Ethernet Controller I210
411
Table 8-9. PCIe Statistic Events Encoding
8.6.4 PCIe Statistic Control Register #5...#8 - GSCL_5_8 (0x5B90 +
4*n[n=0...3]; RW)
These registers control the operation of the statistical counters GSCN_0, GSCN_1, GSCN_2 and GSCN_3
when operating in Leaky Bucket mode:
— GSCL_5 controls operation of GSCN_0.
— GSCL_6 controls operation of GSCN_1.
— GSCL_7 controls operation of GSCN_2.
— GSCL_8 controls operation of GSCN_3.
Transaction Layer Events
Event
Mapping
(Hex)
Description
Bad TLP From LL 0x0
For each cycle, the counter increases by one, if a bad TLP is received (bad CRC,
error reported by AL, misplaced special char, or reset in thI of received tlp).
Requests That Reached Timeout 0x10 Number of requests that reached time out.
NACK DLLP Received 0x20 For each cycle, the counter increases by one, if a message was transmitted.
Replay Happened in Retry-Buffer 0x21
Occurs when a replay happened due to a timeout (not asserted when replay
initiated due to NACK.
Receive Error 0x22
Set when one of the following occurs:
1. Decoder error occurred during training in the PHY. It is reported only when
training ends.
2. Decoder error occurred during link-up or until the end of the current packet
(if the link failed). This error is masked when entering/exiting EI.
Replay Roll-Over 0x23
Occurs when a replay was initiated for more than three times (threshold is
configurable by the PHY CSRs).
Re-Sending Packets 0x24 Occurs when a TLP is resent in case of a completion timeout.
Surprise Link Down 0x25 Occurs when link is unpredictably down (not because of reset or DFT).
LTSSM in L0s in both Rx & Tx 0x30 Occurs when LTSSM enters L0s state in both Tx and Rx.
LTSSM in L0s in Rx 0x31 Occurs when LTSSM enters L0s state in Rx.
LTSSM in L0s in Tx 0x32 Occurs when LTSSM enters L0s state in Tx.
LTSSM in L1 active 0x33
Occurs when LTSSM enters L1-active state (requested from host side).
Note: In case of RECOVERY entries not due to L1 exit, if the host will NAK the
L1 request, there will be false L1 entry counts.
LTSSM in L1 SW 0x34
Occurs when LTSSM enters L1-switch (requested from switch side).
Note: In case of RECOVERY entries not due to L1 exit, if the host will NAK the
L1 request, there will be false L1 entry counts.
LTSSM in Recovery 0x35 Occurs when LTSSM enters recovery state.
Field Bit(s) Initial Value Description
LBC threshold n 15:0 0x0 Threshold for the Leaky Bucket Counter n.
LBC timer n 31:16 0x0 Time period between decrementing the value in Leaky Bucket Counter n.