Data Sheet

Programming Interface — Ethernet Controller I210
409
8.6 PCIe Register Descriptions
8.6.1 PCIe Control - GCR (0x5B00; RW)
8.6.2 PCIe Statistics Control #1 - GSCL_1 (0x5B10; RW)
Field Bit(s) Initial Value Description
Reserved 1:0 0x0 Reserved.
Discard on BME de-
assertion
2 1b When set and BME deasserted, PCIe discards all requests of this function.
Reserved 8:3 0x0
Reserved.
Write 0x0, ignore on read.
Completion Timeout
Resend Enable
90b
1
1. Loaded from PCIe Completion Timeout Configuration Flash word (word 0x15).
When set, enables a resend request after the completion timeout expires.
0b = Do not resend request after completion timeout.
1b = Resend request after completion timeout.
Note: This field is loaded from the Completion Timeout Resend bit in the
Flash.
Reserved 10 0b
Reserved.
Write 0b, ignore on read.
Number of Resends 12:11 11b The number of resends in case of timeout or poisoned.
Reserved 17:13 0x0
Reserved.
Write 0x0, ignore on read.
PCIe Capability Version
(RO)
18 1b
2
2. The default value for this field is read from the PCIe Init Configuration 3 Flash word (address 0x1A) bits 11:10. If these bits are
set to 10b, then this field is set to 1b, otherwise field is reset to zero.
Reports the PCIe capability version supported.
0b = Capability version: 0x1.
1b = Capability version: 0x2.
Reserved 30:19 0x0 Reserved.
DEV_RST In Progress 31 0b
Device Reset in Progress.
This bit is set following device reset assertion (CTRL.DEV_RST = 1b) until
no pending requests exist in PCIe.
The software device driver should wait for this bit to be cleared before re-
initializing the port (Refer to Section 4.3.1).
Field Bit(s) Initial Value Description
GIO_COUNT_EN_0 0 0b Enable PCIe Statistic Counter Number 0.
GIO_COUNT_EN_1 1 0b Enable PCIe Statistic Counter Number 1.
GIO_COUNT_EN_2 2 0b Enable PCIe Statistic Counter Number 2.
GIO_COUNT_EN_3 3 0b Enable PCIe Statistic Counter Number 3.
LBC Enable 0 4 0b When set, statistics counter 0 operates in Leaky Bucket mode.
LBC Enable 1 5 0b When set, statistics counter 1 operates in Leaky Bucket mode.
LBC Enable 2 6 0b When set, statistics counter 2 operates in Leaky Bucket mode.
LBC Enable 3 7 0b When set, statistics counter 3 operates in Leaky Bucket mode.
Reserved 26:8 0x0
Reserved.
Write 0x0, ignore on read.
GIO_COUNT_TEST 27 0b
Test Bit.
Forward counters for testability.