Data Sheet

Programming Interface — Ethernet Controller I210
403
8.4.34 EEPROM Block Base Address – EEBLKBASE (0x1210C; RO)
8.4.35 EEPROM Block End Address – EEBLKEND (0x12110; RO)
8.4.36 Software Flash Burst Control Register - FLSWCTL (0x12048; RW)
Field Bit(s) Init. Description
1st Start Address 10:0 0x000
The base address expressed in words of the first hardware section (EEPROM map),
which is protected from software writes. Loaded from the secured section in the Flash
(word 0x2D).
Reserved 11 Reserved.
2nd Start Address 22:12 0x000
The base address expressed in words of the second hardware section (EEPROM map),
which is protected from software writes. Loaded from the secured section in Flash (word
0x12). This read-only section ends at the shadow RAM ends.
For legacy reasons, it is cleared to 0x000 when there is no second hardware protected
section in the shadow RAM.
Reserved 31:23 Reserved.
Field Bit(s) Init. Description
1st End Address 10:0 0x000
The last address expressed in words of the first hardware section (EEPROM map), which
is protected from software writes. Loaded from the secured section in the Flash (word
0x2C).
For legacy reasons, it is cleared to 0x000 when there is no first hardware protected
section in the shadow RAM.
Reserved 31:11 Reserved
Field Bit(s) Init. Description
ADDR 23:0 0x0
Address in Bytes.
This field is written by software along with CMD to indicate the Flash address to which
the operation (read/write/erase, etc.) is performed. See the command description
following this table.
CMD 27:24 00b
Command.
Indicates which command that should be executed.
CMDV (RO) 28 0b
Last Command was Valid.
When cleared, it indicates that the last command issued was either a reserved
combination (see the following table), or one of the following:
• When count reached zero (except for a general purpose status write)
• When a write burst crosses a Flash page
• When the address to be written is protected (RO)
• When the CNT specified is out of the permitted range (see the following table).
FLBUSY (RO) 29 0b
Flash Busy.
This bit indicates that the Flash is busy processing a Flash transaction and should not be
accessed.
DONE (RO) 30 1b
Single Flash Transaction Done.
This bit clears after the register is written by software and is set back again when the
single Flash transaction was issued to the Flash device.
When writing a burst transaction, the bit is cleared every time software writes
FLSWDATA.
GLDONE (RO) 31 1b
Global Flash Transaction Done.
This bit clears after the register is written by software and is set back again when the all
the Flash transactions were issued to the Flash device. For example, the Flash device
completed all requested read/writes.