Data Sheet

Ethernet Controller I210 — Programming Interface
402
8.4.28 FLASH Read Status Register – FLASHRDST (0x12008; RW)
This register holds the last read status from Flash. This register is reset only at power on or during
LAN_PWR_GOOD assertion.
8.4.29 Flash Block Base Address – FLBLKBASE (0x12100; RO)
8.4.30 Flash Block End Address – FLBLKEND (0x12104; RO)
8.4.31 Flash Firmware Code Update – FLFWUPDATE (0x12108; RW)
8.4.32 Shadow RAM Debug – SHADOWDBG (0x1206C; RW)
8.4.33 EEPROM-Mode Diagnostic - EEDIAG (0x12060; RO)
This register reflects the values of NVM bits influencing the hardware that are not reflected otherwise.
Field Bit(s) Init. Description
Start Address 11:0 0x000
The base address expressed in a 4 KB sector index of the Flash section, which is
protected from software writes. Aligned to 4 KB boundaries. Loaded from the secured
section in Flash (word 0x10).
Reserved 30:12 Reserved.
Field Bit(s) Init. Description
End Address 11:0 0x000
The last 4 KB sector index included in the Flash section, which is protected from
software writes. It is derived by firmware from Max Module Area field extracted from
the new firmware image header (refer to Table 6-14).
A null value in this field means no blocked area.
Reserved 31:12 Reserved
Field Bit(s) Init. Description
Reserved 28:0 Reserved.
AUTHEN-DONE (RO) 29 0x0
Authentication Cycle Done.
Set to 1b when done.
This bit is self-cleared once the update request is set to 1b.
AUT_FAIL (RO) 30 0x0 Authentication failed. Set to 1b when failed.
Update 31 0b
Request authentication of the new secure section written. If the authentication
succeeds, firmware resets itself to load its new code.
This bit is self-cleared, always read as 0b.