Data Sheet

Ethernet Controller I210 —Interconnects
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3.1.4.2 Transaction Types Initiated by the I210
3.1.4.2.1 Data Alignment
Requests must never specify an address/length combination that causes a memory space access to
cross a 4 KB boundary. The I210 breaks requests into 4 KB-aligned requests (if needed). This does not
pose any requirement on software. However, if software allocates a buffer across a 4 KB boundary,
hardware issues multiple requests for the buffer. Software should consider limiting buffer sizes and
base addresses to comply with a 4 KB boundary in cases where it improves performance.
The general rules for packet alignment are as follows:
1. The length of a single request should not exceed the PCIe limit of MAX_PAYLOAD_SIZE for write
and MAX_READ_REQ for read.
2. The length of a single request does not exceed the I210’s internal limitation.
3. A single request should not span across different memory pages as noted by the 4 KB boundary
previously mentioned.
Note: The rules apply to all the I210 requests (read/write, snoop and no snoop).
If a request can be sent as a single PCIe packet and still meet rules 1-3, then it is not broken at a
cache-line boundary (as defined in the PCIe Cache Line Size configuration word), but rather, sent as a
single packet (motivation is that the chipset might break the request along cache-line boundaries, but
the I210 should still benefit from better PCIe use). However, if rules 1-3 require that the request is
broken into two or more packets, then the request is broken at a cache-line boundary.
3.1.4.2.2 Multiple Tx Data Read Requests (MULR)
The I210 supports 6 pipelined requests for transmit data on the port. In general, the 6 requests might
belong to the same packet or to consecutive packets to be transmitted on the LAN port. However, the
following restriction applies: all requests for a packet are issued before a request is issued for a
consecutive packet.
Read requests can be issued from any of the supported queues, as long as the restriction is met.
Pipelined requests might belong to the same queue or to separate queues. However, as previously
noted, all requests for a certain packet are issued (from same queue) before a request is issued for a
different packet (potentially from a different queue).
Table 3-5. Transaction Types Initiated by the Transaction Layer
Transaction type Payload Size FC Type From Client
Configuration Read Request Completion Dword CPLH + CPLD Configuration space
Configuration Write Request Completion - CPLH Configuration space
I/O Read Request Completion Dword CPLH + CPLD CSR
I/O Write Request Completion - CPLH CSR
Read Request Completion Dword/Qword CPLH + CPLD CSR
Memory Read Request - NPH DMA
Memory Write Request <= MAX_PAYLOAD_SIZE
1
1. MAX_PAYLOAD_SIZE supported is loaded from Flash (128 bytes, 256 bytes or 512 bytes). Effective MAX_PAYLOAD_SIZE is defined
according to configuration space register.
PH + PD DMA
Message 64 bytes
2
2. MCTP messages contains payload.
PH INT / PM / Error Unit / LTR