Data Sheet

Programming Interface — Ethernet Controller I210
401
8.4.25 Flash Op-code Register – FLASHOP (0x12054; RO in Secured
Mode)
This register holds the Flash op-codes. This register is reset only at power on or during
LAN_PWR_GOOD assertion. It is loaded by firmware from its own module.
8.4.26 FLASH General Purpose OP-Code Register – FLASHGOP
(0x12058; RO in secured mode)
This register holds the Flash Read/write general purpose op-codes. This register is reset only at power
on or during LAN_PWR_GOOD assertion. It is loaded by firmware from its own module.
8.4.27 Flash Timing Register – FLASHTIME (0x12004; RO in Secured
Mode)
This register holds the timing parameters for Flash access. This register is reset only at power on or
during LAN_PWR_GOOD assertion. It is loaded by firmware from its own module.
NUM_OF_DUMMY 2:1 01b
Indicates the number of dummy bytes that should be provided to the Flash after
providing the address.
FLASH_SPEED 4:3 0b
Indicates the frequency of the clock provided to the Flash.
00b = Clock is 15.125 MHz
01b = Clock is 31.25 MHz.
10b = Clock is 62.5 MHz.
11b = Reserved.
Reserved 5 0 Reserved
SST_MODE 6 1b
When set to 1b,indicates that the current Flash device operates in a 1-byte program for
each Flash access. This mode is the default operating mode as it is supported by all
Flash devices. However, each time the Flash device supports burst writes, clearing this
bit improves Flash write performance.
Reserved 31:7 0x0 Reserved.
Field Bit(s) Init. Description
FLASHERASEOP 7:0 0xC7 Holds the op-code for erasing the entire Flash device.
SUSPENDOP 15:8 0x75 Holds the op-code for suspending the program/erase operation in the Flash.
RESUMEOP 23:16 0x7A Holds the op-code for resuming the program/erase operation that was suspended.
FASTREADOP 31:24 0x0B Holds the op-code that is issued in a Read command when Fast Read Mode Is set.
Field Bit(s) Init. Description
CSDESELECT 3:0 0xB
Indicates the time in cycles of 8 ns that CS should be de-asserted between two
commands. Note that an offset of 16 ns is added to the programmed value. The default
is 104 ns.
Reserved 15:04 0x0 Reserved.
HOLDTIME 31:16 0x00FF
The I210 maintains a hold timer that counts the time that CS is asserted and no
command is issued.
When the timer expires, the CS is de-asserted and the next command starts a new
transaction to Flash.
The time is measured in cycles of 16 ns. The default is 4 µs.
Field Bit(s) Init. Description