Data Sheet

Programming Interface — Ethernet Controller I210
399
8.4.13.1 Management Flash Control Register - FLMNGCTL (0x12038; RW)
8.4.13.2 Management Flash Read Data - FLMNGDATA (0x1203C; RW)
8.4.13.3 Management Flash Read Counter - FLMNGCNT (0x12040; RW)
8.4.14 Flash Security - FL_SECU (0x12114; RO to host, RW to FW)
8.4.15 VPD Diagnostic Register - VPDDIAG (0x5B3C; RO to Host, RW to
FW)
8.4.16 Shadow RAM Information Register - SHADOWINF (0x012068;
RO)
8.4.17 Manageability EEPROM-Mode Control Register – EEMNGCTL
(0x12030; RO to Host, RW to FW)
Note: The transactions performed through this register are directed to/from the internal shadow
RAM. The write data is effectively copied into the Flash device by use of the EEC.FLUPD
command.
8.4.18 Manageability EEPROM-Mode Read/Write Data – EEMNGDATA
(0x12034; RO to host, RW to FW)
8.4.19 Manageability Flash Control Register – FLMNGCTL (0x12038; RO
to host, RW to FW)
See register Software FLASH Burst Control Register - FLSWCTL in Section 8.4.36.
Field Bit(s) Init. Description
Reserved 17:0 0x0 Reserved.
CFG_DONE (RO) 18 0b
Manageability Configuration Cycle of the Port Completed.
This bit indicates that the manageability configuration cycle (configuration of PHY)
completed. It is cleared by hardware on PHY reset events, and it is set to 1b by firmware
to indicate PHY configuration completed.
Note: Software should not try to access the PHY for configuration before this bit is
set.
Reserved 31:19 0x0 Reserved.