Data Sheet

Ethernet Controller I210 — Programming Interface
398
8.4.12.2 Management EEPROM Read/Write data - EEMNGDATA (0x12034; RW)
8.4.13 Management-Flash CSR I/F
The following registers are reserved for firmware access to the serial flash and are not writable by the
host.
CFG_DONE 0
1
18 0b
Configuration cycle is done for port 0 – This bit indicates that configuration cycle
(configuration of SerDes, PHY, PCIe and PLLs) is done for port 0. This bit is set to 1b to
indicate configuration done, and cleared by hardware on any of the reset sources that
causes initialization of the PHY.
Note: Port 0 driver should not try to access the PHY for configuration before this bit is
set.
CFG_DONE 1
1
19 0b
Configuration cycle is done for port 1 – This bit indicates that configuration cycle
(configuration of SerDes, , PCIe and PLLs) is done for port 1. This bit is set to 1b to
indicate configuration done, and cleared by hardware on any of the reset sources that
cause initialization of the PHY.
Note: Port 1 driver should not try to access the PHY for configuration before this bit is
set.
CFG_DONE 2
1
20 0b
Configuration cycle is done for port 2 – This bit indicates that the configuration cycle
(configuration of SerDes, PCIe and PLLs) is done for port 2. This bit is set to 1b to
indicate configuration done, and cleared by hardware on any of the reset sources that
cause initialization of the PHY.
Note: Port 2 driver should not try to access the PHY for configuration before this bit is
set.
CFG_DONE 3
1
21 0b
Configuration cycle is done for port 3 – This bit indicates that the configuration cycle
(configuration of SerDes, PCIe and PLLs) is done for port 3. This bit is set to 1b to
indicate configuration done, and cleared by hardware on any of the reset sources that
cause initialization of the PHY.
Note: Port 3 driver should not try to access the PHY for configuration before this bit is
set.
Reserved 28:22 0x0
Reserved
Write 0, ignore on read.
EEMNGCTL_CL
R_ERR (SC)
29 0b
Clear Timeout Error
A write 1b to the EEMNGCTL.EEMNGCTL_CLR_ERR bit clears the error reported in the
EEMNGCTL.TIMEOUT bit.
TIMEOUT 30 0b
When bit is set to 1b indicates that a transaction timed out while trying to read the
Flash status (Occurs when no Flash exists).
Notes:
1. To clear the bit Firmware should write 1b to the EEMNGCTL.EEMNGCTL_CLR_ERR
bit.
2. Bit is not cleared by Firmware reset.
DONE 31 1b
Transaction Done - This bit is cleared after the Start Write or Start Read bit is set by the
MNG and is set back again when the Flash write or read transaction is done.
Note: Bit is not cleared by Firmware reset.
1. Bit relates to physical port. If LAN Function Swap (FACTPS.LAN Function Sel = 1) is done, Software should poll CFG_DONE bit of
original port to detect end of PHY configuration operation.
Field Bit(s) Initial Value Description
WRDATA 15:0 0x0
Write Data
Data to be written to the Flash.
RDDATA (RO) 31:16 –
Read Data
Data returned from the Flash read.
Field Bit(s) Initial Value Description