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Data Sheet

ManualsBrandsIntel ManualsComputing & OfficeIntel Intel Ethernet Server Adapter I210-T1 - Network adapter 1 Gbps LAN (10/100/1000 Mbps), PCI-Express
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Ethernet Controller I210 — Programming Interface
396
Note: The default values fit to Atmel* Serial Flash Memory devices.
Notes:
1. Register reset on LAN_PWR_GOOD only.
2. Register shared by all functions.
8.4.9 EEPROM Diagnostic - EEDIAG (0x1038; RO)
This register reflects the values of EEPROM bits influencing the hardware that are not reflected
otherwise.
Note: Register shared by all functions.
8.4.10 EEPROM Auto Read Bus Control - EEARBC (0x12024; R/W)
In EEPROM-less implementations, this register is used to program the I210 the same way it should be
programmed if an EEPROM was present.
This register is common to all functions and should be accessed only following access coordination with
the other ports.
Notes:
1. Register reset on LAN_PWR_GOOD only.
2. Register shared by all functions.
Field Bit(s) Initial Value Description
DERASE 7:0 0x0062
Flash Device Erase Instruction
The op-code for the Flash erase instruction.
SERASE 15:8 0x0052
Flash Block Erase Instruction
The op-code for the Flash block erase instruction. Relevant only to Flash
access by manageability.
Reserved 31:16 0x0
Reserved
Write 0 ignore on read.
Field Bit(s) Initial Value Description
VALID_CORE0 0 0b
Valid Write Active to Core 0
Write strobe to Core 0. Firmware/software sets this bit for write access to registers
loaded from EEPROM words in LAN0 section. Software should clear this bit to
terminate the write transaction.
VALID_CORE1 1 0b
Valid Write Active to Core 1
Write strobe to Core 1. Firmware/software sets this bit for write access to registers
loaded from EEPROM words in LAN1 section. Software should clear this bit to
terminate the write transaction.
VALID_COMMON 2 0b
Valid Write Active to Common
Write strobe to Common. Firmware/software sets this bit for write access to
registers loaded from EEPROM words that are common to all sections. Software
should clear this bit to terminate the write transaction.
VALID_PCIE 3 0b
Valid Write Active to PCIe PHY
Write strobe to PCI PHY. Firmware/software sets this bit for write access to registers
loaded from EEPROM words pointed by word 0x10 that are directed to the PCIe phy.
Software should clear this bit to terminate the write transaction.